Semiconductor device, method for manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

Patent metadata

Field	Value
Publication number	US-9916981-B2
Application number	US-201715430769-A
Country	US
Kind code	B2
Filing date	Feb 13, 2017
Priority date	Jul 22, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a silicon carbide layer having a first plane and a second plane;
a first electrode having a first region provided in the silicon carbide layer, a width of a second-plane-side end portion of the first region being less than a width of a first-plane-side end portion of the first region, a first inclination angle of a side surface of the first region with respect to a plane parallel to the first plane being equal to or greater than 60 degrees and equal to or less than 85 degrees;
a second electrode facing the first electrode, the silicon carbide layer being interposed between the second electrode and the first electrode;
a first gate electrode;
a second gate electrode facing the first gate electrode, the first region being interposed between the second gate electrode and the first gate electrode;
a first gate insulating layer provided between the first region and the first gate electrode;
a second gate insulating layer provided between the first region and the second gate electrode;
a first silicon carbide region of a first conductivity type provided in the silicon carbide layer;
a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first plane and between the first region and the first gate insulating layer;
a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first plane and between the first region and the second gate insulating layer;
a fourth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first plane;
a fifth silicon carbide region of the first conductivity type provided between the third silicon carbide region and the first plane and the first region interposed between the fifth silicon carbide region and the fourth silicon carbide region;
a sixth silicon carbide region of the second conductivity type provided between the second-plane-side end portion of the first region and the first silicon carbide region and between the side surface of the first region and the first silicon carbide region and having a higher second-conductivity-type impurity concentration than the second silicon carbide region and the third silicon carbide region; and
a seventh silicon carbide region of the second conductivity type provided between the first silicon carbide region and the sixth silicon carbide region and having a lower second-conductivity-type impurity concentration than the sixth silicon carbide region, a distance between the seventh silicon carbide region and the second plane being less than a distance between the second plane and the second silicon carbide region and a distance between the second plane and the third silicon carbide region.

2. The semiconductor device according to claim 1 ,
wherein a second-conductivity-type impurity concentration of the seventh silicon carbide region is higher than a second-conductivity-type impurity concentration of the second silicon carbide region and the third silicon carbide region.

3. The semiconductor device according to claim 2 ,
wherein the second-conductivity-type impurity concentration of the seventh silicon carbide region is equal to or greater than two times the second-conductivity-type impurity concentration of the second silicon carbide region and the third silicon carbide region.

4. The semiconductor device according to claim 1 ,
wherein the distance between the second plane and the seventh silicon carbide region is less than a distance between the second plane and the first gate insulating layer and a distance between the second plane and the second gate insulating layer.

5. The semiconductor device according to claim 1 ,
wherein the first inclination angle is equal to or greater than 65 degrees and equal to or less than 80 degrees.

6. The semiconductor device according to claim 1 ,
wherein a second inclination angle of a boundary between the seventh silicon carbide region and the first silicon carbide region with respect to the plane parallel to the first plane is equal to or greater than 60 degrees and equal to or less than 85 degrees.

7. The semiconductor device according to claim 6 ,
wherein the second inclination angle is equal to or greater than 65 degrees and equal to or less than 80 degrees.

8. The semiconductor device according to claim 1 ,
wherein the sixth silicon carbide region is in contact with the fourth silicon carbide region and the fifth silicon carbide region.

9. The semiconductor device according to claim 1 ,
wherein a difference between a distance between the first region and the first gate insulating layer and a distance between the seventh silicon carbide region and the first gate insulating layer and a difference between a distance between the first region and the second gate insulating layer and a distance between the seventh silicon carbide region and the second gate insulating layer are equal to or less than 0.1 μm.

10. The semiconductor device according to claim 1 ,
wherein a distance between a first contact point between the first plane and the side surface of the first region close to the first gate insulating layer and the first gate insulating layer and a distance between a second contact point between the first plane and the side surface of the first region close to the second gate insulating layer and the second gate insulating layer are equal to or greater than 0.1 μm and equal to or less than 0.8 μm.

11. The semiconductor device according to claim 1 ,
wherein a distance between a first contact point between the first plane and the side surface of the first region close to the first gate insulating layer and the first gate insulating layer and a distance between a second contact point between the first plane and the side surface of the first region close to the second gate insulating layer and the second gate insulating layer are equal to or greater than 0.3 μm and equal to or less than 0.6 μm.

12. The semiconductor device according to claim 1 ,
wherein the first gate insulating layer and the second gate insulating layer includes silicon oxide.

13. An inverter circuit comprising:
the semiconductor device according to claim 1 .

14. A driving device comprising:
the semiconductor device according to claim 1 .

15. A vehicle comprising:
the semiconductor device according to claim 1 .

16. An elevator comprising:
the semiconductor device according to claim 1 .

17. A method for manufacturing a semiconductor device comprising:
forming a second region of a second conductivity type in a silicon carbide layer including a first region of a first conductivity type and having a first plane and a second plane;
forming two first trenches in the first plane of the silicon carbide layer so as to be deeper than the second region;
forming a second trench in the first plane of the silicon carbide layer between the two first trenches, using a mask member covering the two first trenches as a mask, such that the second trench is deeper than the second region and an inclination angle of a side surface of the second trench with respect to the first plane is equal to or greater than 60 degrees and equal to or less than 85 degrees;
implanting ions in the silicon carbide layer from the side and bottom of the second trench at an angle of 1 degree or less with respect to a line normal to the first plane to forma third region of the second conductivity type;
implanting ions in the silicon carbide layer from the side and bottom

Assignees

• Toshiba Kk

Inventors

• Ohashi Teruyuki
• Kono Hiroshi
• Kanie Souzou
• Shimizu Tatsuo

Classifications

• H10P30/2042 Primary

  into crystalline silicon carbide · CPC title

• H10P30/222 Primary

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title