Semiconductor device

Patent metadata

Field	Value
Publication number	US-9786742-B2
Application number	US-201615067438-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Sep 11, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a SiC layer having a first plane and a second plane;
a gate insulating film provided on the first plane;
a gate electrode provided on the gate insulating film;
a first SiC region of a first conductivity type provided in the SiC layer, and the first SiC region having a portion in contact with the first plane;
a second SiC region of a second conductivity type provided in the SiC layer, the second SiC region provided between the first plane and the first SiC region, the second SiC region having a first part and a second part, the second part being in contact with the first plane, the first part being adjacent to the second part in a first direction, the first direction being parallel to the first plane;
a third SiC region of the first conductivity type provided in the SiC layer, the third SiC region provided between the second SiC region and the first plane, and a part of the third SiC region being in contact with the first plane; and
a fourth SiC region of the first conductivity type provided in the SiC layer, the fourth SiC region provided between the first part of the second SiC region and the gate insulating film, the fourth SiC region being adjacent to the second part of the second SiC region in the first direction in the first plane, the fourth SiC region provided between the first SiC region and the third SiC region in a second direction in the first plane, the second direction being perpendicular to the first direction and being parallel to the first plane, and first-conductivity-type impurity concentration of the fourth SiC region is lower than first-conductivity-type impurity concentration of the third SiC region.

2. The semiconductor device according to claim 1 ,
wherein the fourth SiC region and the third SiC region are in contact with each other in the first plane.

3. The semiconductor device according to claim 1 ,
wherein width of the fourth SiC region interposed between the second SiC regions is gradually reduced in a direction from the first plane to the second plane.

4. The semiconductor device according to claim 1 ,
wherein the second SiC region is provided between the fourth SiC region and the third SiC region in the first plane.

5. The semiconductor device according to claim 1 ,
wherein, when width of the fourth SiC region interposed between the second SiC regions in the first plane is w [μm], the second-conductivity-type impurity concentration of the second SiC region is N A [cm 3 ], the first-conductivity-type impurity concentration of the fourth SiC region is N D [cm −3 ], Vbi is 3.2 [V], q is 1.602×10 −19 [C], ε 0 is 8.854×10 −14 [F/cm], and ε is 9.7, the following inequality is satisfied:

w
≦

2
×
10000
×

2
⁢

ɛ
0

⁢

ɛ
·

V
bi

q

⁢

N
A

+

N
D

N
A

⁢

N
D

.

6. The semiconductor device according to claim 1 ,
wherein the width of the fourth SiC region in the first direction is equal to or less than 1.6 μm.

7. The semiconductor device according to claim 1 ,
wherein density of crystal defects in the fourth SiC region is lower than density of crystal defects in the second SiC region.

8. The semiconductor device according to claim 1 ,
wherein width of the fourth SiC region in the first direction is less than depth of the fourth SiC.

9. The semiconductor device according to claim 1 ,
wherein the first-conductivity-type impurity concentration of the fourth SiC region is substantially equal to the first-conductivity-type impurity concentration of the first SiC region.

10. The semiconductor device according to claim 1 ,
wherein the gate insulating film is a silicon oxide film.

11. A semiconductor device comprising:
a SiC layer having a first plane and a second plane;
a gate insulating film provided on the first plane;
a gate electrode provided on the gate insulating film;
a first SiC region of a first conductivity type provided in the SiC layer;
a second SiC region of a second conductivity type provided in the first SiC region, the second SiC region provided between the first plane and the first SiC region, the second SiC region having a first part and a second part, the second part being in contact with the first plane, the first part being adjacent to the second part in a first direction, the first direction being parallel to the first plane;
a third SiC region of the first conductivity type provided in the second SiC region; and
a fourth SiC region of the first conductivity type provided between the first part of the second SiC region and the gate insulating film, the fourth SiC region being adjacent to the second part of the second SiC region in the first direction, the fourth SiC region provided between the first SiC region and the third SiC region in a second direction, the second direction being perpendicular to the first direction and being parallel to the first plane, and first-conductivity-type impurity concentration of the fourth SiC region is lower than first-conductivity-type impurity concentration of the third SiC region.

12. The semiconductor device according to claim 11 ,
wherein the fourth SiC region and the third SiC region are in contact with each other.

13. The semiconductor device according to claim 11 ,
wherein width of the fourth SiC region interposed between the second SiC regions is gradually reduced in a direction from the first plane to the second plane.

14. The semiconductor device according to claim 11 ,
wherein the second SiC region is provided between the fourth SiC region and the third SiC region.

15. The semiconductor device according to claim 11 ,
wherein, when width of a portion close to the first plane in the fourth SiC region interposed between the second SiC regions is w [μm], the second-conductivity-type impurity concentration of the second SiC region is N A [cm 3 ], the first-conductivity-type impurity concentration of the fourth SiC region is N D [cm −3 ], Vbi is 3.2 [V], q is 1.602×10 −19 [C], ε 0 is 8.854×10 −14 [F/cm], and ε is 9.7, the following inequality is satisfied:

Assignees

• Toshiba Kk

Inventors

• Suzuki Takuma
• Kono Hiroshi

Classifications

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H01L29/1037

  Electricity · mapped topic