‘RDL-First’ packaged microelectronic device for a package-on-package device

Patent metadata

Field	Value
Publication number	US-9911718-B2
Application number	US-201615353552-A
Country	US
Kind code	B2
Filing date	Nov 16, 2016
Priority date	Nov 17, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, at least one redistribution layer includes first interconnect pads on a lower surface and second interconnect pads on an upper surface of the at least one redistribution layer. Interconnect structures are on and extend away from corresponding upper surfaces of the second interconnect pads. A microelectronic device is coupled to an upper surface of the at least one redistribution layer. A dielectric layer surrounds at least portions of shafts of the interconnect structures. The interconnect structures have upper ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.

First claim

What is claimed is:

1. A method for forming a packaged microelectronic device, comprising:
forming at least one redistribution layer having an inner region and an outer region outside the inner region;
the forming of the at least one redistribution layer comprising forming first interconnect pads in both the inner region and the outer region at a lower surface and second interconnect pads in the outer region at an upper surface of the at least one redistribution layer;
forming interconnect structures on and extending away from corresponding upper surfaces of the second interconnect pads in the outer region;
coupling a microelectronic device to an upper surface of the at least one redistribution layer in the inner region;
forming a reinforcing layer with a stiffener material on the interconnect structures;
forming a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device; and
the interconnect structures having upper ends thereof protruding above an upper surface of the dielectric layer a distance.

2. The method according to claim 1 , wherein the forming of the at least one redistribution layer comprises:
obtaining a carrier substrate having an upper surface and a lower surface opposite the upper surface;
adhering an adhesive layer to the upper surface of the carrier substrate;
applying a metal layer to an upper surface of the adhesive layer; and
patterning the first interconnect pads out of the metal layer including forming an area array layout for a subset of the first interconnect pads in the inner region.

3. The method according to claim 2 , wherein:
the metal layer is a metal foil; and
the adhesive layer is an adhesive tape.

4. The method according to claim 1 , wherein the interconnect structures include plating-formed posts plated in part on the upper surfaces of the second interconnect pads.

5. The method according to claim 1 , wherein the interconnect structures include wire bond wires bonded to the upper surfaces of the second interconnect pads.

6. The method according to claim 1 , wherein the interconnect structures are first interconnect structures, the packaged microelectronic device further comprising:
forming second interconnect structures on and extending away from an upper surface of the microelectronic device;
the forming of the dielectric layer including surrounding at least portions of shafts of the second interconnect structures; and
the second interconnect structures having upper ends thereof protruding above the upper surface of the dielectric layer the distance.

7. The method according to claim 6 , wherein the packaged device is a first packaged device, the method further comprising coupling a second packaged microelectronic device to the protrusions of the first and the second interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

8. The method according to claim 1 , wherein the packaged device is a first packaged device, the method further comprising coupling a second packaged microelectronic device to the protrusions of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

9. The method according to claim 1 , wherein the upper ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding bases of the interconnect structures.

10. The method according to claim 1 , wherein portions of the stiffener material wick-up at least a portion of the interconnect structures.

11. A packaged microelectronic device, comprising:
at least one redistribution layer having an inner region and an outer region outside the inner region;
the at least one redistribution layer comprising first interconnect pads in both the inner region and the outer region on a lower surface and second interconnect pads in the outer region on an upper surface of the at least one redistribution layer;
interconnect structures on and extending away from corresponding upper surfaces of the second interconnect pads in the outer region;
a microelectronic device coupled to an upper surface of the at least one redistribution layer in the inner region;
a reinforcing layer formed with a stiffener material on the interconnect structures;
a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device; and
the interconnect structures having upper ends thereof protruding above an upper surface of the dielectric layer a distance.

12. The packaged microelectronic device according to claim 11 , wherein the first interconnect pads include an area array layout for a subset of the first interconnect pads in the inner region.

13. The packaged microelectronic device according to claim 11 , wherein the interconnect structures include plating-formed posts plated in part on the upper surfaces of the second interconnect pads.

14. The packaged microelectronic device according to claim 11 , wherein the interconnect structures include wire bond wires bonded to the upper surfaces of the second interconnect pads.

15. The packaged microelectronic device according to claim 11 , wherein the interconnect structures are first interconnect structures, the packaged microelectronic device further comprising:
second interconnect structures on and extending away from an upper surface of the microelectronic device;
the dielectric layer formed to surround at least portions of shafts of the second interconnect structures; and
the second interconnect structures having upper ends thereof protruding above the upper surface of the dielectric layer the distance.

16. The packaged microelectronic device according to claim 11 , wherein the packaged microelectronic device is a first packaged microelectronic device, the first packaged microelectronic device being coupled to a second packaged microelectronic device, the second packaged microelectronic device coupled to the protrusions of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.

17. The packaged microelectronic device according to claim 11 , wherein the upper ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding bases of the interconnect structures.

18. The packaged microelectronic device according to claim 11 , wherein:
portions of the stiffener material wick-up at least portions of the interconnect structures; and
the stiffener material is a polymeric material.

Assignees

• Invensas Corp

Inventors

• Prabhu Ashok S
• Katkar Rajesh

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title