III-V photonic integration on silicon

Patent metadata

Field	Value
Publication number	US-9910220-B2
Application number	US-201514794106-A
Country	US
Kind code	B2
Filing date	Jul 8, 2015
Priority date	Jan 20, 2006
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Photonic integrated circuits on silicon are disclosed. By bonding a wafer of HI-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.

First claim

What is claimed is:

1. An article comprising:
(1) a semiconductor substrate comprising;
a first substrate having a major surface that defines a first plane;
a first layer, the first layer comprising single-crystal silicon, the first layer including a first waveguide;
a first cladding region; and
a second cladding region;
wherein the first waveguide is located between the first cladding region and the second cladding region such that they are coplanar in a second plane that is parallel with the first plane, and wherein the first waveguide is dimensioned and arranged to guide light along a first direction in the second plane;

(2) a compound semiconductor structure comprising a first compound semiconductor layer and at least one quantum well; and
(3) a bonded interface that is characterized by a lattice mismatch, the first waveguide and the compound semiconductor structure being joined at the bonded interface;
wherein the at least one quantum well and the first waveguide are evanescently coupled through the bonded interface.

2. The article of claim 1 further comprising (4) an electrical device, the electrical device being at least partially formed in the first semiconductor layer.

3. The article of claim 1 further comprising (4) an electrical device, the electrical device being at least partially formed in the compound semiconductor structure.

4. The article of claim 1 wherein the semiconductor substrate comprises single-crystal silicon.

5. The article of claim 1 wherein at least one of the first cladding region and second cladding region is filled with a material selected from the group consisting of air, silicon oxide, silicon oxynitride, and silicon nitride.

6. The article of claim 1 wherein the compound semiconductor structure further includes a second compound semiconductor layer that comprises the at least one quantum well, and wherein the first compound semiconductor layer and the first waveguide are joined at the bonded interface.

7. The article of claim 1 wherein the compound semiconductor structure comprises a first separated confinement heterostructure (SCH) and a second SCH, and wherein the at least one quantum well is between the first SCH and the second SCH.

8. The article of claim 1 further comprising:
(4) a first laser having a first gain region, the compound semiconductor structure comprising the first gain region, wherein the first laser provides a first signal on the first waveguide;
(5) a second laser having a second gain region, the compound semiconductor structure comprising the second gain region, wherein the second laser provides a second signal on a second waveguide, and wherein the first layer includes the second waveguide;
(6) an electronic circuit that is operative for driving at least one of the plurality of lasers, wherein the first layer comprises at least a portion of the electronic circuit; and
(7) a wavelength-division-multiplexed (WDM) output;
wherein the first waveguide and the second waveguide are optically coupled such that the WDM output includes the first signal and the second signal.

9. An article comprising:
(1) a first silicon layer resident on a first surface of a substrate, the first surface defining a first plane, the first silicon layer comprising single-crystal-silicon, and the first silicon layer comprising a first waveguide that is operative for conveying a light signal along a direction within a second plane that is parallel with the first plane;
(2) a compound semiconductor structure comprising a first compound first compound semiconductor layer and a second compound semiconductor layer that includes at least one quantum well; and
(3) a bonded interface that is characterized by a lattice mismatch, the first compound semiconductor layer and the first silicon layer being joined at the bonded interface;
wherein the at least one quantum well and the first waveguide are evanescently coupled through the bonded interface.

10. The article of claim 9 further comprising (4) an electrical device, the electrical device being at least partially formed in the first semiconductor layer.

11. The article of claim 10 , wherein the electrical device includes at least one transistor.

12. The article of claim 9 further comprising (4) an electrical device, the electrical device being at least partially formed in the compound semiconductor structure.

13. The article of claim 9 further comprising:
(4) a first separated confinement heterostructure (SCH) and a second SCH, wherein a first region of the compound semiconductor structure comprises the first SCH, the second SCH, and a gain region, and wherein the second compound semiconductor layer is between the first SCH and the second SCH; and
(5) a first distributed Bragg reflector (DBR) and a second DBR, each of the first DBR and second DBR being operative for causing reflection within the first waveguide;
wherein the first region is between the first DBR and second DBR; and
wherein the first DBR, second DBR, the first waveguide, and the first region of the compound semiconductor structure collectively define a laser.

14. The article of claim 13 wherein the laser is tunable.

15. An article comprising:
(1) a substrate comprising;
a first surface that defines a first plane; and
a first layer disposed on the first surface, the first layer comprising single-crystal silicon, the first layer including a first waveguide that is operative for guiding a light signal along a first direction within a second plane that is parallel with the first plane;
(2) a first photonic device that is disposed on the substrate in a first region, the first photonic device comprising:
(a) the first waveguide;
(b) a compound semiconductor structure comprising a first compound semiconductor layer and at least one quantum well; and
(c) a first bonding interface that is characterized by a lattice mismatch, the first waveguide and the compound semiconductor structure being joined at the first bonding interface;
wherein the at least one quantum well and the first waveguide are evanescently coupled through the bonding interface; and

(3) a first electronic device that is disposed on the substrate in a second region;
wherein the first electronic device and first photonic device are electrically coupled.

16. The article of claim 15 wherein the electrical device comprises at least a portion of the first layer.

17. The article of claim 15 wherein the photonic device is selected from the group consisting of a laser, a modulator, and a photodetector.

18. The article of claim 17 wherein the electrical device comprises an integrated-circuit element.

19. The article of claim 15 further comprising:
a first semiconductor layer; and
a second bonding interface;
wherein first semiconductor layer and the first compound semiconductor structure are joined at the second bonding interface.

20. The article of claim 19 wherein second bonding interface is characterized by a lattice mismatch.

Assignees

• Univ California

Inventors

• Bowers John E

Classifications

• H01S5/18341

  Intra-cavity contacts · CPC title

• H01S5/0217

  Removal of the substrate · CPC title

• Y02P70/521

  Cross-Sectional Technologies · mapped topic

• H01L27/146

  Electricity · mapped topic

• G02B6/12002

  Three-dimensional structures · CPC title