Multilayer capacitors, method for making multilayer capacitors

US9908817B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9908817-B2
Application numberUS-201213528544-A
CountryUS
Kind codeB2
Filing dateJun 20, 2012
Priority dateJun 2, 2009
Publication dateMar 6, 2018
Grant dateMar 6, 2018

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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The invention provides a stacked capacitor configuration comprising subunits each with a thickness of as low as 20 microns. Also provided is combination capacitor and printed wire board wherein the capacitor is encapsulated by the wire board. The invented capacitors are applicable in micro-electronic applications and high power applications, whether it is AC to DC or DC to AC, or DC to DC.

First claim

Opening claim text (preview).

The embodiment of the invention in which an exclusive property or privilege is claimed is defined as follows: 1. A capacitor device comprising: an array of individual thin-film capacitor units wherein each unit includes a first electrode and second electrode separated by a dielectric layer; a first thin lead in electrical communication with first electrodes in the array of individual thin-film capacitors; a second thin lead in electrical communication with second electrodes in the array of individual thin-film capacitors; and a liquid phase binder to coat the capacitor array, wherein said binder integrally molds the component thin-film capacitors to each other; wherein a dried coating formed by the liquid phase binder encapsulates exterior surfaces of the device including portions of a top surface of the device except for external lead attachment regions; wherein all first electrodes of the stacked capacitors are interconnected with the first lead and all second electrodes of the array of thin-film capacitors are interconnected with the second lead wherein within the capacitor device forming a monolith, each pair of the first electrodes are adjacent to one another with the first lead in communication with each pair of first electrodes, and each pair of second electrodes are adjacent to one another with the second lead in communication with each pair of second electrodes; wherein only the external lead attachment regions protrude from the capacitor monolith which forms a pore-less monolith. 2. The device recited in claim 1 further comprising a buffer layer between the first thin lead and the dielectric layer of the capacitor. 3. The device as recited in claim 2 wherein the buffer layer comprises an electrically conductive film deposited on the first thin lead. 4. The device as recited in claim 1 further comprising three external leads extending from the capacitor monolith. 5. The device as recited in claim 4 wherein the first external lead is electrically connected to a first region of the capacitor construct, the second external lead is electrically connected to a second region of the capacitor construct, and the third external lead is electrically connected to a third region of the capacitor construct, wherein the first region comprises less than half of the first electrodes, second region comprises all second electrodes, and the third region comprises a remainder of the first electrodes; wherein each region is electrically insulated. 6. The device as recited in claim 1 wherein the array of individual thin-film capacitors forms a stack having a first end and a second end and at least one of the thin leads emanates from the stack between the first end and the second end. 7. The device as recited in claim 6 wherein a first capacitor defining the first end of the stack includes an exposed lead attachment region and a second capacitor defining the second end of the stack is removably attached to the exposed lead attachment region of the first capacitor. 8. The device as recited in claim 1 wherein the capacitors comprising the capacitor array are integrally molded to each other to form a monolith, wherein the dried flexible binder encapsulates exterior surfaces of the device, including at least a portion of a top surface of each capacitor forming the monolith. 9. The capacitor as recited in claim 8 wherein the monolith is between about 20 and 50 micrometers thick. 10. The device as recited in claim 1 wherein the capacitor has a radius of flexibility of about 3 mm. 11. The device as recited in claim 1 wherein each capacitor comprising the capacitor array is flexible so as to allow the device to conform to an adjacent surface having a radius of flexibility of as low as about 1 mm. 12. The device as recited in claim 1 wherein at least one of said capacitors has a thickness of less than 20 microns.

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What does patent US9908817B2 cover?
The invention provides a stacked capacitor configuration comprising subunits each with a thickness of as low as 20 microns. Also provided is combination capacitor and printed wire board wherein the capacitor is encapsulated by the wire board. The invented capacitors are applicable in micro-electronic applications and high power applications, whether it is AC to DC or DC to AC, or DC to DC.
Who is the assignee on this patent?
Ma Beihai, Balachandran Uthamalingam, Uchicago Argonne Llc
What technology area does this patent fall under?
Primary CPC classification C04B35/491. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue Mar 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).