Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9905657-B2
Application number	US-201715408719-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Jan 20, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first insulating layer over a substrate;
forming a first oxide insulating layer over the first insulating layer;
forming a first oxide semiconductor layer over the first oxide insulating layer;
forming a second insulating layer over the first oxide semiconductor layer;
forming a third insulating layer by etching the second insulating layer with a first mask so that a first part of the first oxide semiconductor layer is exposed;
forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer;
forming a second conductive layer by performing etch-back treatment on the first conductive layer so that a second part of the first oxide semiconductor layer is exposed, wherein the second conductive layer comprises a region in contact with a side surface of the third insulating layer;
removing the third insulating layer;
forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the second conductive layer as a second mask so that the first insulating layer is exposed;
forming a fourth insulating layer over the first insulating layer and the second conductive layer;
forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer;
forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the second conductive layer with a third mask;
forming a third oxide insulating layer, a seventh insulating layer, and a third conductive layer over the sixth insulating layer and the second oxide semiconductor layer; and
forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the third conductive layer.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the first conductive layer is formed by a CVD method.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese, nitrogen, and oxygen.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein an angle between the side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.

6. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first insulating layer over a substrate;
forming a first oxide insulating layer over the first insulating layer;
forming a first oxide semiconductor layer over the first oxide insulating layer;
forming a second insulating layer over the first oxide semiconductor layer;
forming a third insulating layer by etching the second insulating layer with a first mask, wherein the third insulating layer has a frame shape when seen from a direction perpendicular to a surface of the substrate;
forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer;
forming a second conductive layer by performing etch-back treatment on the first conductive layer, wherein the second conductive layer comprises a region in contact with inside and outside surfaces of a frame of the third insulating layer;
removing the third insulating layer;
forming a third conductive layer by etching the second conductive layer with a second mask, wherein the third conductive layer has a rectangular shape when seen from the direction perpendicular to the surface of the substrate;
forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the third conductive layer as a third mask;
forming a fourth insulating layer over the first insulating layer and the third conductive layer;
forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer;
forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the third conductive layer with a fourth mask;
forming a third oxide insulating layer over the sixth insulating layer and the second oxide semiconductor layer;
forming a seventh insulating layer over the third oxide insulating layer;
forming a fourth conductive layer over the seventh insulating layer; and
forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the fourth conductive layer.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the first conductive layer is formed by a CVD method.

8. The method for manufacturing a semiconductor device according to claim 6 , wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese, nitrogen, and oxygen.

9. The method for manufacturing a semiconductor device according to claim 6 , wherein an angle between a side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.

10. The method for manufacturing a semiconductor device according to claim 6 , wherein a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.

Assignees

• Semiconductor Energy Lab

Inventors

• Endo Yuta
• Suzawa Hideomi
• Hanaoka Kazuya
• Sasagawa Shinya
• Okamoto Satoru

Classifications

• H01L29/42384

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/78693

  Electricity · mapped topic

• H01L27/14616

  Electricity · mapped topic