Group III-nitride compound heterojunction tunnel field-effect transistors and methods for making the same

Patent metadata

Field	Value
Publication number	US-9905647-B2
Application number	US-201514925542-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Oct 28, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A tunnel field-effect transistor device includes a p-type GaN source layer, an n-type GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (In x Ga 1-x N) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration.

First claim

What is claimed is:

1. A tunnel field-effect transistor comprising:
a source-layer including p-type GaN;
a drain-layer including n-type GaN; and
an interlayer interfaced between the source-layer and the drain-layer, wherein the interlayer includes an InN layer, wherein the tunnel field-effect transistor further includes a gate, wherein the source-layer, the drain-layer, the interlayer and the gate are arranged in an in-line configuration; and
wherein a thickness of the interlayer is based on a width of the gate, wherein the thickness of the interlayer is based on a relationship between energy band and tunneling distance that an interlayer thickness of 1.7 nanometers for a gate width of 20 nanometers provides for maximum on-current density.

2. The tunnel field-effect transistor of claim 1 , wherein the thickness of the interlayer is within a range of 0.1 to 3.0 nanometers.

3. A tunnel field-effect transistor comprising:
a source-layer including p-type GaN;
a drain-layer including n-type GaN; and
an interlayer interfaced between the source-layer and the drain-layer, wherein the interlayer includes an InN layer and a graded InGaN layer, wherein the tunnel field-effect transistor further includes a gate, wherein the source-layer, the drain-layer, the interlayer and the gate are arranged in an in-line configuration; and
wherein a thickness of the interlayer is based on a width of the gate, wherein the thickness of the interlayer is based on a relationship between energy band and tunneling distance that an interlayer thickness of 1.7 nanometers for a gate width of 20 nanometers provides for maximum on-current density.

4. The tunnel field-effect transistor of claim 3 , wherein the InGaN layer is linearly graded about its thickness.

5. The tunnel field-effect transistor of claim 4 , wherein the InGaN layer is linearly graded about its thickness as follows: x is linearly increases from 0 to 1 for In x Ga 1-x N.

6. The tunnel field-effect transistor of claim 5 , wherein the thickness of the graded InGaN layer is based on a thickness of the InN layer, wherein the thickness of the graded InGaN layer is based on an observed relationship that a graded InGaN layer thickness of 0.6 nanometers provides for maximum on-current density.

7. A tunnel field-effect transistor comprising:
a source-layer including p-type GaN;
a drain-layer including n-type GaN; and
an interlayer interfaced between the source-layer and the drain-layer, wherein the interlayer includes an InGaN layer and a graded InGaN layer,
wherein the tunnel field-effect transistor further includes a gate, wherein the source-layer, the drain-layer, the interlayer and the gate are arranged in an in-line configuration; and wherein a thickness of the interlayer is based on a width of the gate, wherein the thickness of the interlayer is based on a relationship between energy band and tunneling distance that an interlayer thickness of 1.7 nanometers for a gate width of 20 nanometers provides for maximum on-current density.

8. The tunnel field-effect transistor of claim 7 , wherein a In mole faction of the InGaN layer is selected based on tunnel field-effect transistor achieving a switching slope of less than 60 millivolts per decade.

Assignees

• Univ Notre Dame Du Lac

Inventors

• Fay Patrick
• Li Wenjun
• Jena Debdeep

Classifications

• H01L29/78

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/0895 Primary

  Electricity · mapped topic

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D62/141

  Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs · CPC title