Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Patent metadata

Field	Value
Publication number	US-9905505-B2
Application number	US-201514924256-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 31, 2007
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

First claim

What is claimed is:

1. An assembly, comprising:
a chip including an integrated circuit;
a casing including an integrated circuit including plural active elements and including:
an upper portion formed on a side of said chip;
a lower portion formed on another side of said chip; and
a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of said upper portion and inner sidewalls of said lower portion;

a system board configured to be electrically connected to the casing;
plural through-wafer vias (TWVs) for electrically connecting said integrated circuit of said chip and said integrated circuit of said casing; and
a plurality of cards connected to said casing for electrically connecting said casing to said system board,
wherein the plurality of cards comprises:
an upper card electrically connecting said upper portion of said casing to said system board; and
a lower card electrically connecting said lower portion of said casing to said system board, and

wherein, in a cross-sectional view, opposing edges of the upper card are located between vertical planes defined by said outer sidewalls of said upper portion of said casing, said outer sidewalls of said upper portion of said casing are located between vertical planes defined by opposing outer sidewalls of said lower portion of said casing, and said opposing outer sidewalls of said lower portion of said casing are located between vertical planes defined by opposing edges of the lower card.

2. The assembly of claim 1 , wherein said upper and lower cards are connected to said upper and lower portions of said casing, respectively, by plural solder balls which are aligned with said plural through-wafer vias such that said plural through-wafer vias are electrically connected to said upper and lower cards.

3. The assembly of claim 2 , wherein said chip further comprises a silicon die formed on said integrated circuit of said chip, said plural through-wafer vias being formed in silicon pillars of said silicon die.

4. The assembly of claim 3 , wherein said chip including said integrated circuit comprises plural chips including plural integrated circuits, said plural chips forming a chip stack.

5. The assembly of claim 4 , further comprising:
a fluid channel formed between an upper surface of a silicon die formed on a first chip in said chip stack, and a lower surface of a second chip formed above said first chip in said chip stack.

6. The assembly of claim 5 , wherein said upper and lower portions of said casing form a coolant inlet for transporting coolant into said chip stack, and a coolant outlet for transporting said coolant out of said chip stack.

7. The assembly of claim 1 , wherein said through-wafer vias comprise first vias that run through said chip and electrically connect said integrated circuit of said chip to said upper casing, and second vias that run through said chip and electrically connect said integrated circuit of said chip to said lower casing.

8. The assembly of claim 7 , wherein said first and second vias being alternately formed such that an interleaving input/output (I/O) is formed above and below said chip.

9. The assembly of claim 1 , wherein said integrated circuit of said chip comprises a microprocessor circuit.

10. The assembly of claim 4 , wherein said integrated circuits of said plural chips and said integrated circuit of said casing collectively form a three dimensional integrated circuit.

11. The assembly of claim 4 , wherein said plural chips in said chip stack comprise different integrated circuits.

12. The assembly of claim 1 , wherein said integrated circuit of casing comprises an integrated circuit including plural active elements formed on said upper portion of said casing and an integrated circuit including plural active elements formed on said lower portion of said casing.

13. The assembly of claim 1 , wherein said TWVs are included in said upper and lower portions of said casing.

14. An assembly, comprising:
a chip including an integrated circuit;
a casing including an integrated circuit and including:
an upper portion formed on a side of said chip;
a lower portion formed on another side of said chip; and
a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of said upper portion and inner sidewalls of said lower portion;

a system board configured to be electrically connected to the casing;
plural through-wafer vias (TWVs) for electrically connecting said integrated circuit of said chip and said integrated circuit of said casing; and
a plurality of cards connected to said casing for electrically connecting said casing to said system board,
wherein said plural through-wafer vias are included in said upper and lower portions of said casing,
wherein the plurality of cards comprises:
an upper card electrically connecting said upper portion of said casing to said system board; and
a lower card electrically connecting said lower portion of said casing to said system board, and

wherein, in a cross-sectional view, opposing edges of the upper card are located between vertical planes defined by said outer sidewalls of said upper portion of said casing, said outer sidewalls of said upper portion of said casing are located between vertical planes defined by opposing outer sidewalls of said lower portion of said casing, and said opposing outer sidewalls of said lower portion of said casing are located between vertical planes defined by opposing edges of the lower card.

15. The assembly of claim 14 , wherein said upper and lower cards are connected to said upper and lower portions of said casing, respectively, by plural solder balls which are aligned with said plural through-wafer vias such that said plural through-wafer vias are electrically connected to said upper and lower cards.

16. The assembly of claim 15 , wherein said chip further comprises a silicon die formed on said integrated circuit of said chip, said plural through-wafer vias being formed in silicon pillars of said silicon die.

17. The assembly of claim 16 , wherein said chip including said integrated circuit comprises plural chips including plural integrated circuits, said plural chips forming a chip stack.

18. The assembly of claim 14 , wherein said integrated circuit of casing comprises an integrated circuit including plural active elements formed on said upper portion of said casing and an integrated circuit including plural active elements formed on said lower portion of said casing.

19. The assembly of claim 1 , wherein, in the cross-sectional view, an edge of the opposing edges of the upper card faces and is spaced apart from a surface of said system board.

Assignees

• IBM

Inventors

• Bernstein Kerry
• Brunschwiler Thomas
• Michel Bruno

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title