Array substrate and manufacturing method for the same

Patent metadata

Field	Value
Publication number	US-9905470-B2
Application number	US-201514890654-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Oct 10, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

An array substrate and a manufacturing method therefor. The method comprises: patterning a first metal layer by means of a first photomask so as to form a gate electrode ( 21 ) and a first conductor ( 22 ) which are arranged at an interval; patterning a semiconductor layer ( 40 ) and a gate insulating layer ( 30 ) by means of a second photomask so as to form a through hole ( 23 ) which Is exposed out of the first conductor ( 22 ); patterning the semiconductor layer ( 40 ) by means of the gate electrode ( 21 ) and the first conductor ( 22 ) so as to form a first channel region ( 43 ) and a second channel region ( 44 ) which are arranged at an interval; and patterning a second metal layer by means of a third photomask so as to form a source electrode ( 51 ), a drain electrode ( 52 ) and a second conductor ( 53 ) which are arranged at intervals, wherein the second conductor ( 53 ) is in contact with the first conductor ( 22 ) via the through hole ( 23 ). By means of the manufacturing method for the array substrate, the semiconductor layer ( 40 ) and the gate insulating layer ( 30 ) are patterned by means of a photomask, so that the production costs of the array substrate are reduced, bridging between the first conductor ( 22 ) and the second conductor ( 53 ) is realized using a relatively simple method, and the production efficiency of the array substrate is further improved.

First claim

What is claimed is:

1. A manufacturing method for an array substrate, comprising following steps:
providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer through a first mask in order to form a gate electrode and a first conductive layer which are disposed at an interval;
depositing a gate insulation layer on the gate electrode and the first conductive layer;
depositing a semiconductor layer on the gate insulation layer, and patterning the semiconductor layer and the gate insulation layer through a second mask in order to form a through hole for revealing the first conductive layer;
patterning the semiconductor layer through the gate electrode and the first conductive layer in order to form a first channel region and a second channel region which are disposed at an interval, wherein the first channel region is correspondingly located above the gate electrode, and the second channel region is correspondingly located above the first conductive layer; and
depositing a second metal layer on the first channel region and the second channel region, and patterning the second metal layer through a third mask in order to form a source electrode, a drain electrode and a second conductive layer which are disposed at intervals, wherein, the second conductive layer is contacted with the first conductive layer through the through hole;
wherein, the step of patterning the semiconductor layer and the gate insulation layer through a second mask in order to form a through hole for revealing the first conductive layer is:
coating a first photoresist layer on the semiconductor layer;
performing a front exposing and developing to the first photoresist layer through the second mask;
wet etching the first photoresist layer, the semiconductor layer and the gate insulation layer after developing; and
removing the first photoresist layer after wet etching in order to form the through hole for revealing the first conductive layer at the semiconductor layer and the gate insulation layer;
wherein, the step of patterning the semiconductor layer through the gate electrode and the first conductive layer in order to form a first channel region and a second channel region is:
coating a second photoresist layer on the semiconductor layer;
performing back exposing and developing to the second photoresist layer through the gate electrode and the first conductive layer;
wet etching the second photoresist layer and the semiconductor layer after developing; and
removing the second photoresist layer after wet etching in order to form the first channel region and the second channel region in the semiconductor layer.

2. The manufacturing method according to claim 1 , wherein,
the step of depositing a gate insulation layer on the gate electrode and the first conductive layer specifically is: depositing the gate insulation layer on the gate electrode and the first conductive layer through a plasma enhanced chemical vapor deposition (PECVD) method; and
the step of depositing a semiconductor layer on the gate insulation layer specifically is: depositing the semiconductor layer on the gate insulation layer through a physical vapor deposition (PVD) method.

3. The manufacturing method according to claim 1 , wherein, a material of the semiconductor layer is indium gallium zinc oxide.

4. A manufacturing method for an array substrate, comprising following steps:
providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer through a first mask in order to form a gate electrode and a first conductive layer which are disposed at an interval;
depositing a gate insulation layer on the gate electrode and the first conductive layer;
depositing a semiconductor layer on the gate insulation layer, and patterning the semiconductor layer and the gate insulation layer through a second mask in order to form a through hole for revealing the first conductive layer;
patterning the semiconductor layer through the gate electrode and the first conductive layer in order to form a first channel region and a second channel region which are disposed at an interval, wherein the first channel region is correspondingly located above the gate electrode, and the second channel region is correspondingly located above the first conductive layer; and
depositing a second metal layer on the first channel region and the second channel region, and patterning the second metal layer through a third mask in order to form a source electrode, a drain electrode and a second conductive layer which are disposed at intervals, wherein, the second conductive layer is contacted with the first conductive layer through the through hole.

5. The manufacturing method according to claim 4 , wherein,
the step of depositing a gate insulation layer on the gate electrode and the first conductive layer specifically is: depositing the gate insulation layer on the gate electrode and the first conductive layer through a plasma enhanced chemical vapor deposition (PECVD) method; and
the step of depositing a semiconductor layer on the gate insulation layer specifically is: depositing the semiconductor layer on the gate insulation layer through a physical vapor deposition (PVD) method.

6. The manufacturing method according to claim 4 , wherein, the step of patterning the semiconductor layer and the gate insulation layer through a second mask in order to form a through hole for revealing the first conductive layer is:
coating a first photoresist layer on the semiconductor layer;
performing a front exposing and developing to the first photoresist layer through the second mask;
wet etching the first photoresist layer, the semiconductor layer and the gate insulation layer after developing; and
removing the first photoresist layer after wet etching in order to form the through hole for revealing the first conductive layer at the semiconductor layer and the gate insulation layer.

7. The manufacturing method according to claim 4 , wherein, the step of patterning the semiconductor layer through the gate electrode and the first conductive layer in order to form a first channel region and a second channel region is:
coating a second photoresist layer on the semiconductor layer;
performing back exposing and developing to the second photoresist layer through the gate electrode and the first conductive layer;
wet etching the second photoresist layer and the semiconductor layer after developing; and
removing the second photoresist layer after wet etching in order to form the first channel region and the second channel region in the semiconductor layer.

8. The manufacturing method according to claim 4 , wherein, a material of the semiconductor layer is indium gallium zinc oxide.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Shi Longqiang

Classifications

• H10P76/403

  for lift-off processes · CPC title

• H10P76/202 Primary

  for lift-off processes · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• G02F1/1333

  Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) · CPC title

• G02F2001/1635

  the pixel comprises active switching elements, e.g. TFT · CPC title