Thin film transistor, display panel having the same and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9356153-B2
Application number	US-201414452261-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Oct 18, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A thin film transistor includes a bottom gate electrode, a top gate electrode and an active pattern. The top gate electrode includes a transparent conductive material and overlaps with the bottom gate electrode. A boundary of the bottom gate electrode and a boundary of the top gate electrode are coincident with each other in a cross-sectional view. The active pattern includes a source portion, a drain portion and a channel portion disposed between the source portion and the drain portion. The channel portion overlaps with the bottom gate electrode and the top gate electrode.

First claim

What is claimed is:

1. A thin film transistor comprising:
a bottom gate electrode;
a top gate electrode comprising a transparent conductive material and overlapping with the bottom gate electrode; and
an active pattern comprising a source portion, a drain portion and a channel portion disposed between the source portion and the drain portion, wherein the channel portion overlaps with the bottom gate electrode and the top gate electrode,
wherein the top gate electrode and the bottom gate electrode start in a same location relative to a first direction and end in a same location relative to the first direction, and
wherein the top gate electrode and the channel portion start in a same location relative to a second direction, which is different from the first direction, and end in a same location relative to the second direction.

2. The thin film transistor of claim 1 , wherein the bottom gate electrode comprises an opaque metal.

3. The thin film transistor of claim 2 , wherein the active pattern is transparent.

4. The thin film transistor of claim 2 , wherein the active pattern comprises an oxide semiconductor, and wherein the source and drain portions are deoxidized portions of the oxide semiconductor.

5. The thin film transistor of claim 4 , wherein a thickness of the active pattern is about 500 Å.

6. The thin film transistor of claim 3 , wherein the active pattern comprises an amorphous silicon, and wherein a thickness of the active pattern is about 100 Å.

7. The thin film transistor of claim 1 , further comprising:
a substrate on which the bottom gate electrode is disposed;
a first insulation layer disposed between the bottom gate electrode and the active pattern, wherein the first insulation layer is configured to insulate the bottom gate electrode; and
a second insulation pattern disposed between the active pattern and the top gate electrode, wherein the second insulation pattern is configured to insulate the top gate electrode.

8. The thin film transistor of claim 7 , wherein a boundary line of the second insulation pattern is substantially the same as a boundary line of the top gate electrode in a plan view.

9. The thin film transistor of claim 1 , wherein a boundary line between the channel portion and the source portion and a boundary line between the channel portion and the drain portion are substantially coincident with a boundary line of the bottom gate electrode.

10. The thin film transistor of claim 1 , wherein a deviation of a skew is less than about 0.5 μm,
wherein the skew is defined as a miss-align distance between the bottom gate electrode and the top gate electrode, and
wherein the deviation of the skew is defined as a value of a smallest skew subtracted from a biggest skew.

11. A display panel comprising:
a gate line;
a data line crossing the gate line;
a first electrode disposed in a pixel area which is defined by the gate line and the data line; and
a thin film transistor electrically connected to the gate line, the data line and the first electrode,
wherein the thin film transistor comprises:
a bottom gate electrode electrically connected to the gate line,
a top gate electrode comprising a transparent conductive material and overlapping with the bottom gate electrode, and
an active pattern comprising a source portion electrically connected to data line, a drain portion electrically connected to the first electrode and a channel portion disposed between the source portion and the drain portion, wherein the channel portion overlaps with the bottom gate electrode and the top gate electrode,
further comprising a connecting electrode which electrically connects the top gate electrode to the gate line, wherein the connecting electrode comprising a same material as the first electrode.

12. The display panel of claim 11 , wherein the bottom gate electrode comprises an opaque metal, wherein the active pattern is transparent and comprises an oxide semiconductor, and wherein the source and drain portions of the active pattern are deoxidized portions of the oxide semiconductor.

13. The display panel of claim 12 , further comprising:
a substrate on which the gate line and the bottom gate electrode are disposed;
a first insulation layer disposed between the bottom gate electrode and the active pattern, wherein the first insulation layer is configured to insulate the bottom gate electrode;
a second insulation pattern disposed between the active pattern and the top gate electrode, wherein the second insulation pattern is configured to insulate the top gate electrode;
a third insulation layer disposed on the thin film transistor, wherein the third insulation layer is configured to insulate thin film transistor; and
a fourth insulation layer disposed on the third insulation layer, wherein the data line is disposed between the third insulation layer and the fourth insulation layer.

14. The display panel of claim 11 , wherein a first contact hole is disposed through the third insulation layer, a second contact hole disposed through the third insulation layer and the fourth insulation layer, a third contact hole disposed through the third insulation layer and the fourth insulation layer, a fourth contact hole disposed through the first insulation layer, the third insulation layer and the fourth insulation layer, wherein the data line is electrically connected to the source portion of the active pattern through the first contact hole, wherein the first electrode is electrically connected to the drain portion of the active pattern through the second contact hole, and wherein the connecting electrode is electrically connected to the top gate electrode through the third contact hole, and electrically connected to the gate line through the fourth contact hole.

15. The display panel of claim 11 , wherein a deviation of a skew is less than about 0.5 μm, wherein the skew is defined as a miss-align distance between the bottom gate electrode and the top gate electrode, and wherein the deviation of the skew is defined as a value of a smallest skew subtracted from a biggest skew.

16. A method of manufacturing a thin film transistor comprising:
forming a bottom gate electrode on a substrate, wherein the bottom gate electrode comprises an opaque metal;
forming a first insulation layer on the substrate on which the bottom gate electrode is formed;
sequentially forming an active layer, a second insulation layer and a top gate layer on the first insulation layer, wherein the top gate layer comprises a transparent conductive material;
forming a photoresist pattern corresponding to the bottom gate electrode, wherein the forming the photoresist pattern comprises:
coating a photoresist composition on the top gate layer, and
applying a back exposure to the photoresist composition, wherein the back exposure includes irradiating light in a direction from the substrate to the photoresist composition; and
forming a top gate electrode and a second insulation pattern by etching a portion of the top gate layer and a portion of the second insulation layer which are not covered by the photoresist pattern, and wherein portions of the active layer are exposed by the forming of the top gate electrode and the second insulation pattern,
wherein the top gate electrode and the bottom gate electrode start in a same location relative to a first direction and end in a same location relative to the first direction, and
wherein the top gate electrode and the channel portion start in a same location relative to a second direction, which is different from the first direction, and end in a same locatio

Assignees

• Samsung Display Co Ltd

Inventors

• Khang Yoon-Ho
• Kim Dong-Jo
• Kang Su-Hyoung
• Lee Yong-Su

Classifications

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10D30/6734 Primary

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title