Methods of fabricating a semiconductor device having a via structure and an interconnection structure

Patent metadata

Field	Value
Publication number	US-9905458-B2
Application number	US-201514802086-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Dec 3, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Methods of fabricating a semiconductor device include forming a lower interlayer insulating layer and a conductive base structure, and forming a middle interlayer insulating layer covering the lower interlayer insulating layer and the conductive base structure. The methods include etching the middle interlayer insulating layer to form a via hole and an interconnection trench vertically aligned with the via hole, and forming a via barrier layer on inner walls of the via hole and an interconnection barrier layer on inner walls and a bottom of the interconnection trench, the via barrier layer not being formed on an upper surface of the conductive base structure The methods include forming a via plug on the via barrier layer to fill the via hole, forming a seed layer on the interconnection trench and the via plug, forming an interconnection electrode on the seed layer, and forming an interconnection capping layer on the interconnection electrode.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a lower interlayer insulating layer and a conductive base structure, upper surfaces of the lower interlayer insulating layer and the conductive base structure being coplanar;
forming a middle interlayer insulating layer covering the lower interlayer insulating layer and the conductive base structure;
forming,
(i) a via hole vertically extending through the middle interlayer insulating layer to expose the upper surface of the conductive base structure, and
(ii) an interconnection trench vertically aligned with the via hole;

forming,
a via barrier layer on inner walls of the via hole, and
an interconnection barrier layer on inner walls and a bottom of the interconnection trench, the via barrier layer not being formed on the upper surface of the conductive base structure;

forming a via plug on the via barrier layer to fill the via hole;
forming a seed layer on the interconnection barrier layer and an upper surface of the via plug;
forming an interconnection electrode on the seed layer; and
forming an interconnection capping layer on the interconnection electrode.

2. The method of claim 1 , wherein the conductive base structure comprises:
a base electrode, and
a base barrier layer surrounding the base electrode.

3. The method of claim 2 , wherein an upper surface of the base electrode is not covered by the base barrier layer.

4. The method of claim 1 , wherein the via barrier layer and the interconnection barrier layer comprise at least one selected from TaN, TiN, and Mn.

5. The method of claim 1 , wherein the forming the via barrier layer comprises:
conformally forming a barrier material layer on the inner walls of the via hole and the upper surface of the exposed conductive base structure; and
removing the barrier material layer formed on the upper surface of the conductive base structure.

6. The method of claim 5 , wherein the removing the barrier material layer on the upper surface of the conductive base structure comprises performing an Ar plasma sputtering process.

7. The method of claim 1 , wherein the upper surface of the via plug is lower than the bottom of the interconnection trench.

8. The method of claim 1 , wherein the via, plug comprises at least one selected from Co and Ru.

9. The method of claim 1 , wherein
the interconnection capping layer is not formed on an upper surface of the middle interlayer insulating layer,
the interconnection capping layer protrudes from an upper surface of the interconnection electrode, and
the interconnection capping layer has an upper surface higher than the upper surface of the middle interlayer insulating layer.

10. The method of claim 1 , wherein the interconnection capping layer comprises at least one selected from Ru and Co.

11. The method of claim 1 , further comprising:
forming a lower stopper layer between the lower interlayer insulating layer and the middle interlayer insulating layer.

12. The method of claim 11 , further comprising:
forming an upper stopper layer on the interconnection capping layer; and
forming an upper interlayer insulating layer on the upper stopper layer.

13. The method of claim 1 , further comprising:
conformally forming a liner layer between the interconnection barrier layer and the seed layer.

14. The method of claim 13 , wherein the liner layer comprises at least one selected from Co and Ru.

15. A method of fabricating a semiconductor device, the method comprising:
forming a lower interlayer insulating layer and a base structure, upper surfaces of the lower interlayer insulating layer and the base structure being coplanar;
forming a lower stopper layer covering the lower interlayer insulating layer and the base structure;
forming a middle interlayer insulating layer on the lower stopper layer;
forming,
(i) a via hole vertically extending through the middle interlayer insulating layer and the lower stopper layer, and
(ii) an interconnection trench vertically aligned with the via hole;

forming a via plug filling the via hole without forming a barrier layer on sidewalls or a bottom of the via hole;
forming an interconnection barrier layer on an upper surface of the via plug and inner walls and a bottom of the interconnection trench;
forming a liner layer on the interconnection barrier layer;
forming a seed layer on the liner layer;
forming an interconnection electrode on the seed layer; and
forming an interconnection capping layer on the interconnection electrode.

16. A method of manufacturing a semiconductor device, comprising:
forming a middle interlayer insulating layer over a base structure, the base structure being within a lower interlayer insulating layer;
etching the middle interlayer insulating layer to form (i) a via hole extending through the middle interlayer insulating layer to expose the base structure, and (ii) an interconnection trench aligned over the via hole so as to form opposing steps in conjunction with the via hole;
forming a via plug filling the via hole without forming a seed layer in the via hole;
forming a barrier layer on a bottom of the interconnection trench, the opposing steps, and at least an uppermost portion of inner walls of the via hole; and
sequentially forming a liner layer, a seed layer, an interconnection electrode and an interconnection capping layer, the liner layer, the seed layer, the interconnection electrode and the interconnection capping layer collectively filling the interconnection trench.

17. The method of claim 16 , wherein the forming the barrier layer includes not forming the barrier layer on a remaining portion of the inner walls of the via hole.

18. The method of claim 16 , wherein:
the forming the via plug includes performing a chemical vapor deposition process, and
the forming the interconnection electrode includes performing a plating process.

19. The method of claim 16 , wherein
the forming the barrier layer includes performing a self-forming process, the self-forming process including not forming the barrier layer on an upper surface of the base structure.

20. The method of claim 16 , wherein
the forming the barrier layer is performed after the forming the via plug, and
the barrier layer contacts an upper surface of the via plug.

Assignees

• Siew Yongkong
• Park Seongho
• Samsung Electronics Co Ltd

Inventors

• Siew Yongkong
• Park Seongho

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title