Three dimensional integrated circuit electrostatic discharge protection and prevention test interface

Patent metadata

Field	Value
Publication number	US-9900970-B2
Application number	US-201514975951-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Dec 17, 2012
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.

First claim

We claim:

1. A method of providing electrostatic discharge protection comprising the steps of:
(a) providing a loadboard assembly electrically connected to a plurality of input/output channels;
(b) providing a socket assembly adaptable to accept an integrated circuit (IC) package, the socket assembly in contact with the loadboard assembly;
(c) placing an IC package within the socket assembly; and
(d) forcing voltage on ones of the plurality of input/output channels to dissipate charges resident on the IC package to thereby provide electrostatic discharge protection.

2. The method of claim 1 wherein steps (a)-(d) are performed before testing of the IC package.

3. The method of claim 1 wherein the forced voltage is positive and the dissipated charges are negative.

4. The method of claim 1 wherein the forced voltage is negative and the dissipated charges are positive.

5. The method of claim 1 wherein the step of placing the IC package within the socket assembly further comprises electrically contacting an interposer of the IC package to connect the IC package to an input/output ground channel of the socket, the ground channel having a resistance to dissipate charges on the IC package.

6. The method of claim 1 wherein the step of contacting the IC package with the interposer further comprises electrically contacting an interposer of the IC package to connect the IC package to an input/output power channel of the socket, the power channel having a resistance to dissipate charges on the IC package.

7. The method of claim 1 , wherein the step of placing the IC package within the socket assembly includes:
confronting a top surface of a material of a mold encasing the IC with a top of the socket assembly; and
contacting a ball grid array at a bottom of the IC with interconnection pins within the socket assembly, the interconnection pins contacting the input/output channels.

8. The method of claim 7 , wherein the interconnection pins extend upwards from a surface of a material at a bottom of the socket assembly.

9. A system to provide electrostatic discharge protection to an integrated circuit (IC) package comprising:
a loadboard assembly electrically connected to a plurality of input/output channels, the loadboard assembly having a loadboard printed circuit board (PCB) and a plurality of ground pins;
a socket assembly adapted to accept an IC package having a ball grid array (BGA), the socket assembly having a plurality of interconnection pins coupled to respective ones of the plurality of ground pins, the interconnection pins configured to contact the BGA when the socket assembly accepts the IC package; and
wherein when the socket assembly accepts the IC package, voltage is forced on ones of the plurality of input/output channels to dissipate charges resident on the IC package to provide electrostatic discharge protection.

10. The system of claim 9 wherein the IC package further comprises an interposer, an array of control collapse chip connection bumps on one side of the interposer and connected to respective through silicon vias which are electrically connected to an array of μbumps on an opposing side of the interposer, the μthumps adaptable to provide an electrical connection between the substrate and the IC package.

11. The system of claim 9 wherein the forced channel is selected from the group consisting of a ground channel having a high resistance and a power channel having a high resistance.

12. The system of claim 9 wherein the socket assembly further includes a metal layer therein for shielding the IC package from charges on the loadboard assembly, thereby avoiding inducement of charges on the IC package.

13. The system of claim 12 wherein the socket assembly further includes insulative portions between the plurality of ground pins and the metal layer to provide a shielding effect between the socket assembly and the IC package.

14. The system of claim 9 , wherein the socket assembly includes:
a top of the socket assembly configured for confronting a top surface of a material of a mold encasing the IC.

15. The system of claim 14 , wherein the socket assembly is configured so that when the top of the socket assembly confronts the top surface of the material of the mod encasing the IC, the BGA of the IC contacts respective interconnection pins of the socket assembly.

16. A socket assembly comprising:
a grounding loadboard electrically connected to a plurality of input/output channels; and
a socket case adaptable to accept an integrated circuit (IC) package having a package substrate and a ball grid array (BGA) adjacent the package substrate, the socket case enclosing:
a conductive plate,
a socket base, and
a plurality of pogo pins configured to make electrical contact with the BGA of the IC package,

wherein the conductive plate includes a conductive material and can mate with any type of socket base,
wherein the grounding loadboard includes routing circuitry to short all signal traces to ground traces to disperse electrostatic discharge current.

17. The socket assembly of claim 16 , wherein the conductive material is selected from the group consisting of nickel alloys, copper alloys, aluminum, and combinations thereof.

18. The socket assembly of claim 16 , wherein the routing circuitry of the grounding loadboard provides connections for interfacing to a plurality of tester ground channels or test head ground channels.

19. The system of claim 16 , wherein the socket case has a top configured to confront the top surface of the material of a mold encasing the IC, while the BGA of the IC contacts respective pogo pins of the socket assembly.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Mill Jer
• Peng Ching Nen
• Lin Hung Chih
• Chen Hao

Classifications

• G01R1/36

  Overload-protection arrangements or circuits for electric measuring instruments · CPC title

• G01R1/07378

  using an intermediate adapter, e.g. space transformers (G01R1/07371 takes precedence) · CPC title

• H05F3/02 Primary

  by means of earthing connections · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H05K2201/07

  Electric details · CPC title