Chopper stabilized amplifier

Patent metadata

Field	Value
Publication number	US-9899974-B2
Application number	US-201615293675-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 16, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A main amplifier generates an output signal S OUT according to a difference between first and second voltages VP and VN. A first gm amplifier is arranged as a differential input stage. A second, fully differential, gm amplifier amplifies a voltage difference between its non-inverting and inverting input terminals, and outputs a differential current signal I 3N /I 3P via its inverting and non-inverting output terminals. An integrator integrates a differential input current I 4P /I 4N input via its non-inverting and inverting input terminals, and samples and holds the signal every predetermined period, to generate a differential voltage signal. A first selector is arranged as an upstream stage of the second gm amplifier, and outputs the differential input signal without change or otherwise after swapping. A second selector is arranged as a downstream stage of the second gm amplifier, and outputs the signal I 3N /I 3P output from the second gm amplifier without change or otherwise after swapping.

First claim

What is claimed is:

1. A chopper stabilized amplifier comprising:
a non-inverting input pin structured to receive a first voltage;
an inverting input pin structured to receive a second voltage;
a main amplifier structured to generate an output signal according to a difference between the first voltage and the second voltage; and
a correction circuit,
wherein the main amplifier comprises:
a differential input stage structured to generate a first current signal, wherein the differential input stage includes a first gm amplifier having a non-inverting input terminal connected to the non-inverting input pin and an inverting input terminal connected to the inverting input pin; and
an output stage structured to receive the first current signal so as to generate the output signal of the main amplifier,

wherein the correction circuit comprises:
a second gm amplifier configured as a fully differential amplifier structured to amplify a voltage difference between its non-inverting input terminal and its inverting input terminal, so as to output a differential current signal from its inverting output terminal and its non-inverting output terminal;
an integrating circuit structured to integrate a differential input current input to its non-inverting input terminal and its inverting input terminal, structured to sample and hold the current integrated for a predetermined period, and structured to generate a differential voltage signal;
a first selector arranged as an upstream stage of the second gm amplifier, so as to switch a state between: (i) a first state in which the non-inverting input pin and the inverting input pin are respectively connected to the inverting input terminal and the non-inverting input terminal of the second gm amplifier; and (ii) a second state in which the non-inverting input pin and the inverting input pin are respectively connected to the non-inverting input terminal and the inverting input terminal of the second gm amplifier;
a second selector arranged downstream from the second gm amplifier, so as to switch a state between: (i) a first state in which the inverting output terminal and the non-inverting output terminal of the second gm amplifier are respectively connected to the inverting input terminal and the non-inverting input terminal of the integrating circuit; and (ii) a second state in which the inverting output terminal and the non-inverting output terminal of the second gm amplifier are respectively connected to the non-inverting input terminal and the inverting input terminal of the integrating circuit; and
a third gm amplifier structured to convert the differential voltage signal generated by the integrating circuit into a second current signal, and superimpose the second current signal on the first current signal;

wherein each of the first selector and the second selector is controlled according to a first clock signal,
and wherein the integrating circuit is controlled according to a second clock signal,
and wherein edges of the first clock signal are shifted from edges of the second clock signal.

2. The chopper stabilized amplifier according to claim 1 , wherein the integrating circuit comprises:
an integrator structured to integrate a differential input current input to the non-inverting input terminal and the inverting input terminal, so as to generate the differential voltage signal; and
a sample-and-hold circuit structured to sample and hold the differential voltage signal generated by the integrator.

3. The chopper stabilized amplifier according to claim 1 , wherein each of the first gm amplifier and the third gm amplifier is configured as a fully differential amplifier,
and wherein the second current signal configured as a differential signal is superimposed on the second current signal configured as a differential signal.

4. The chopper stabilized amplifier according to claim 1 ,
wherein the integrating circuit is controlled such that the integrating circuit is set to a hold state at an edge timing of the first clock signal.

5. The chopper stabilized amplifier according to claim 1 ,
wherein the integrating circuit is controlled such that the integrating circuit performs a sampling operation in a period in which the first clock is stable.

6. The chopper stabilized amplifier according to claim 1 ,
wherein the second clock signal has a period T B which is an integer multiple of a period of the first clock signal.

7. The chopper stabilized amplifier according to claim 6 , wherein the second clock signal has a period T B that is twice the period of the first clock signal.

8. The chopper stabilized amplifier according to claim 7 , wherein each edge of the second clock is shifted by ⅛ of the period thereof T B /8 with respect to an edge of the first clock signal.

9. The chopper stabilized amplifier according to claim 1 , wherein the second gm amplifier comprises a first transistor and a second transistor, each of which is configured as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor),
wherein a source of each of the first transistor and the second transistor is connected to a common tail current source,
and wherein the second gm amplifier outputs currents that respectively flow through the first transistor and the second transistor.

10. The chopper stabilized amplifier according to claim 2 , wherein each of the first selector and the sample-and-hold circuit comprises a plurality of CMOS switches,
and wherein each of the plurality of CMOS switches included in the first selector is smaller than each of the plurality of CMOS switches included in the sample-and-hold circuit.

11. The chopper stabilized amplifier according to claim 1 , wherein each of the first selector and the second selector comprises a plurality of CMOS switches,
and wherein each of the plurality of CMOS switches included in the first selector is smaller than each of the plurality of CMOS switches included in the second selector.

12. The chopper stabilized amplifier according to claim 1 , wherein the first selector comprises a plurality of CMOS switches,
and wherein each of the plurality of CMOS switches comprises a P-channel MOSFET and an N-channel MO SFET, each of which is configured such that a product of a channel width W and a channel length L thereof is smaller than 1 μm 2 .

13. The chopper stabilized amplifier according to claim 12 , wherein each CMOS switch comprises a P-channel MOSFET and an N-channel MOSFET, each of which has the same size.

14. The chopper stabilized amplifier according to claim 1 , further comprising a frequency divider circuit structured to divide a frequency of the first clock signal so as to generate the second clock signal,
wherein the frequency divider circuit comprises a D flip-flop,
wherein the D flip-flop comprises a plurality of CMOS switches,
and wherein, among the CMOS switches, a part that is arranged between an input terminal and an output terminal of the D flip-flop comprises an N-channel MOSFET having a channel length that is greater than a channel length of an N-channel MOSFET of the other part that is arranged in a different region of the D flip-flop.

15. The chopper stabilized amplifier according to claim 1 , monolithically integrated on a single semiconductor substrate.

16. A chopper stabilized amplifier comprising:
a non-inverting input pin that receives a first voltage;
an inverting input pin that receives a second voltage;
a main amplifier that generates an output signal according to a difference between the first voltage and the second voltage; and
a correction circuit,
wherein the main amplif

Assignees

• Rohm Co Ltd

Inventors

• Horiuchi Sachito
• Nomura Naohiro

Classifications

• H03F2203/45444

  the CMCL comprising a sample and hold circuit · CPC title

• H03F2203/45014

  the addition of two signals being made in the tail circuit of a differential amplifier for producing the common mode signal · CPC title

• H03F2203/45116

  Feedback coupled to the input of the differential amplifier · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F3/393 Primary

  with field-effect devices · CPC title