Fast-settling capacitive-coupled amplifiers

Patent metadata

Field	Value
Publication number	US-9294049-B2
Application number	US-201414180639-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 16, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Fast-settling capacitive-coupled amplifiers are disclosed. The amplifiers use two Capacitive Coupled paths embedded in a Multipath Hybrid Nested Miller Compensation topology. One path is a direct high frequency path and the other path is a slower stabilization path. This combination results in a flat frequency response to and through the chopper frequency, and a fast settling response. Various exemplary embodiments are disclosed, including operational amplifier and instrumentation amplifier configurations.

First claim

What is claimed is:

1. A differential amplifier system comprising:
a chopper free signal path having a first differential amplifier with a first differential amplifier output coupled to a differential amplifier system output, the first differential amplifier having a first differential amplifier input capacitively coupled to a differential amplifier system input, the chopper free signal path not having any choppers therein; and
a chopper signal path coupled between the differential amplifier system input and the differential amplifier system output, the chopper signal path having a first chopper having an input coupled to the differential amplifier system input and an output capacitively coupled to an input of a second chopper, the output of the second chopper being coupled through an integrator to the differential amplifier system output.

2. The differential amplifier system of claim 1 further comprised of a third chopper coupled between the differential input of the first differential amplifier and the input of the second chopper.

3. The differential amplifier system of claim 1 wherein each side of a differential input to the first differential amplifier and each side of a differential input to the second chopper is coupled to a respective reference voltage through a resistor, and coupled to the respective reference voltage through a pair of diodes coupled in parallel, the pair of diodes being connected with opposite directions of conduction to limit a magnitude of a voltage difference between the respective reference voltage and the respective side of the respective differential input.

4. The differential amplifier system of claim 1 wherein a clock signal for the first chopper is capacitively coupled to the first chopper.

5. The differential amplifier system of claim 1 further comprising a differential amplifier system feedback input, the differential amplifier system feedback input being capacitively coupled to the differential input of the first differential amplifier, the differential amplifier system feedback input also being coupled to an input of a third chopper, the third chopper having an output capacitively coupled to the differential input of the second chopper.

6. The differential amplifier system of claim 5 wherein the first and third choppers have a clock input capacitively coupled to the respective chopper.

7. The differential amplifier system of claim 5 further comprising a voltage divider coupled between the amplifier system output and the differential amplifier system feedback input.

8. A differential amplifier system comprising:
a first chopper having an input coupled to a differential amplifier system input;
a first differential amplifier having an input capacitively coupled to an output of the first chopper;
a second chopper having an input coupled to an output of the first differential amplifier;
an output of the second chopper being coupled to a differential amplifier system output;
a third chopper having an input capacitively coupled to the differential amplifier system input;
an output of the third chopper being coupled as an input to an integrator; and
an output of the integrator being coupled to the input of the second chopper
each side of a differential input to the first differential amplifier and each side of a differential input to the second chopper is coupled to a respective reference voltage through a resistor, and coupled to the respective reference voltage through a pair of diodes coupled in parallel, the pair of diodes being connected with opposite directions of conduction to limit a magnitude of a voltage difference between the respective reference voltage and the respective side of the respective differential input.

9. The differential amplifier system of claim 8 wherein the integrator is a differential amplifier coupled as an integrator, and further comprised of auto-zeroing circuitry for auto-zeroing the differential amplifier coupled as an integrator.

10. The differential amplifier system of claim 8 wherein the first chopper has a clock signal capacitively coupled to the first chopper.

11. The differential amplifier system of claim 8 further comprised of a fourth chopper coupled between the differential input of the first differential amplifier and the differential input of the third chopper.

12. The differential amplifier system of claim 11 further comprising a differential amplifier system feedback input, the differential amplifier system feedback input being capacitively coupled to the differential input of the third chopper, the differential amplifier system feedback input also being coupled to a fifth chopper, an output of the fifth chopper being capacitively coupled to the differential input of the first differential amplifier.

13. The differential amplifier system of claim 12 further comprising a voltage divider coupled between the differential output of the differential amplifier system and the amplifier system feedback input.

14. The differential amplifier system of claim 8 further comprising a differential amplifier system feedback input, the differential amplifier system feedback input being capacitively coupled to the differential input of the third chopper, the differential amplifier system feedback input also being coupled to an input of a fourth chopper, an output of the fourth chopper being capacitively coupled to the differential input of the first differential amplifier.

15. The differential amplifier system of claim 14 wherein the first and fourth choppers have a capacitively coupled clock input.

16. The differential amplifier system of claim 14 further comprising a voltage divider coupled between the differential amplifier system output and the feedback system input.

17. A differential amplifier system comprising:
a differential amplifier system input;
a first differential amplification path, the first differential amplification path being capacitively coupled to the differential amplifier system input, the first amplification path being coupled through a first differential amplifier to a differential amplifier system output, the first differential amplifier having at least first and second first differential amplifier stages, the first differential amplification path not having any choppers therein;
a second differential amplification path, the second differential amplification path being coupled to the differential amplifier system input through a first chopper, an output of the first chopper being capacitively coupled to an input of a second differential amplifier, the output of the second differential amplifier being coupled to a second chopper, an output of the second chopper being coupled to the input of an integrator, the output of the integrator being coupled to the input of a third differential amplifier, the output of the third differential amplifier being coupled to the input of the second stage of the first differential amplifier, the differential amplifier system having hybrid-nested Miller compensation.

18. The differential amplifier system of claim 17 wherein the first chopper has a clock input capacitively coupled to a clock signal.

19. The differential amplifier system of claim 17 wherein each side of a differential input to the first differential amplifier and each side of the differential input to the second differential amplifier is coupled to a respective reference voltage through a resistor, and coupled to the respective reference voltage through a pair of diodes coupled in parallel, the pair of diodes being connected with opposite dire

Assignees

• Maxim Integrated Products

Inventors

• Huijsing Johan Hendrik
• Fan Qinwen
• Makinwa Kofi Afolabi Anthony
• Fu Daihong
• Wu Jun
• Zhou Lixia

Classifications

• H03F2203/45458

  the CSC comprising one or more capacitors · CPC title

• H03F3/45071

  with semiconductor devices only · CPC title

• H03F1/14 Primary

  by use of neutralising means · CPC title

• H03F2200/459

  Ripple reduction circuitry being used in an amplifying circuit · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title