Semiconductor structure

Patent metadata

Field	Value
Publication number	US-9899523-B2
Application number	US-201514594159-A
Country	US
Kind code	B2
Filing date	Jan 11, 2015
Priority date	Dec 3, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a plurality of gate structures disposed on a substrate;
a plurality of source/drain regions disposed in the substrate at two sides of the plurality of gate structures; and
a plurality of dislocations disposed in one of the plurality of source/drain regions which is between and directly adjacent to two of the plurality of gate structures, and wherein the plurality of dislocations are asymmetrical to each other relating to a vertical middle axis of the one of the plurality of source/drain regions where the plurality of dislocations are disposed.

2. The semiconductor structure according to claim 1 , wherein one of the plurality of dislocations is more severe than another one of the plurality of dislocations.

3. The semiconductor structure according to claim 1 , wherein one of the plurality of dislocations extends a larger distance than another one of the plurality of dislocations does.

4. The semiconductor structure according to claim 1 , further comprising a plurality of fin structures disposed on the substrate, wherein the plurality of source/drain regions are located in one of the plurality of fin structures.

5. The semiconductor structure according to claim 4 , wherein a region is defined on the substrate, and two of the plurality of fin structures closest to an edge of the region have a greater width than those of other fin structures.

6. The semiconductor structure according to claim 5 , wherein one of the plurality of dislocations far from the edge of region is more severe than another one of the plurality of dislocations near the edge of the region.

7. The semiconductor structure according to claim 5 , further comprising a plurality of first shallow trench isolations arranged alternatively with the plurality of fin structures.

8. The semiconductor structure according to claim 7 , wherein the region is encompassed by a second shallow trench isolation, and a depth of the second shallow trench isolation is greater than depths of the plurality of first shallow trench isolations.

9. The semiconductor structure according to claim 5 , further comprising a plurality of epitaxial layers disposed in one of the plurality of fin structures where the plurality of source/drain regions are disposed, wherein each of the plurality of source/drain regions is disposed in each of the plurality of epitaxial layers.

10. The semiconductor structure according to claim 9 , wherein two epitaxial layers in the plurality of fin structures closest to the edge of the region have larger size than the plurality of epitaxial layers in other fin structures.

11. The semiconductor structure according to claim 9 , further comprising a buffer layer disposed between the plurality of epitaxial layers and the plurality of fin structures.

12. The semiconductor structure according to claim 11 , wherein the buffer layer has a substantially curved shape in its cross-section.

13. The semiconductor structure according to claim 12 , wherein the buffer layer has a uniform thickness.

14. The semiconductor structure according to claim 12 , wherein the buffer layer directly surrounds and contacts the plurality of epitaxial layers and is conformally with an edge of the epitaxial layer.

15. The semiconductor structure according to claim 12 , wherein the plurality of dislocations do not penetrate through the buffer layer.

16. The semiconductor structure according to claim 1 , wherein one of the plurality of source/drain regions comprises a P-type dopant.

17. The semiconductor structure according to claim 1 , wherein the plurality of dislocations in one source/drain region at one side of one of the plurality of gate structures is asymmetrical to the plurality of dislocations in one source/drain region at other side of the gate structure relating to an axis of the gate structure.

18. The semiconductor structure according to claim 1 , further comprising:
a plurality of fin structures disposed on the substrate, wherein the plurality of source/drain regions are located in one of the plurality of fin structures at two sides of the gate structure;
a plurality of epitaxial layers disposed in one of the plurality of fin structures, wherein each source/drain region is disposed in each epitaxial layer; and
a buffer layer disposed between and directly contacts bottom surface and sidewalls of each epitaxial layer and each fin structure, wherein the plurality of dislocations does not penetrate into the buffer layer.

19. A semiconductor structure, comprising:
a plurality of gate structures disposed on a substrate;
a plurality of source/drain regions disposed in the substrate at two sides of the plurality of gate structures; and
a plurality of dislocations completely disposed in one of the plurality of source/drain regions which is between two of the plurality of gate structures, and wherein the plurality of dislocations are asymmetrical to each other relating to a vertical middle axis of the one of the plurality of source/drain regions where the plurality of dislocations are disposed.

Assignees

• United Microelectronics Corp

Inventors

• Shen Wen Jiun
• Liu Chia Jong
• Chang Chung Fu
• Wu Yen Liang
• Lu Man Ling
• Chen yi wei
• Li Jhen Cyuan

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/7847

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/7843

  Electricity · mapped topic