Three-dimensional semiconductor memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9899411-B2
Application number	US-201715414345-A
Country	US
Kind code	B2
Filing date	Jan 24, 2017
Priority date	Sep 11, 2012
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

First claim

What is claimed is:

1. A method for fabricating a three-dimensional (3D) semiconductor memory device, the method comprising:
forming a multi-layered structure including sacrificial layers and insulating layers alternately and repeatedly stacked on a substrate;
forming an opening penetrating the multi-layered structure such that the opening exposes the substrate;
forming a lower semiconductor layer filling a lower region of the opening;
forming a vertical insulator and an upper semiconductor pattern in the opening having the lower semiconductor layer;
patterning the multi-layered structure to form trenches exposing the substrate such that the trenches are spaced apart from the opening;
removing the sacrificial layers exposed by the trenches to form gate regions;
selectively etching the lower semiconductor layer exposed by at least a lowermost one of the gate regions to form a lower semiconductor pattern having a recessed region defined by incline-surfaces inclined with respect to a top surface of the substrate; and
forming gate patterns in the gate regions, respectively.

2. The method as claimed in claim 1 , wherein forming the lower semiconductor layer includes performing a selective epitaxial growth process using the substrate exposed by the opening as a seed.

3. The method as claimed in claim 1 , wherein selectively etching the lower semiconductor layer includes performing a gas phase etching process or a chemical dry etching process using a reaction gas containing a halogen element.

4. The method as claimed in claim 1 , wherein a maximum width of the lower semiconductor pattern is greater than a maximum width of the upper semiconductor pattern.

5. The method as claimed in claim 1 , wherein a minimum width of the lower semiconductor pattern is less than a lower width of the upper semiconductor pattern.

6. The method as claimed in claim 1 , wherein a vertical thickness of a lowermost one of the gate patterns is less than a maximum width of the lower semiconductor pattern.

7. The method as claimed in claim 1 , wherein:
the lower semiconductor pattern is formed of silicon; and
the incline-surfaces are {111} crystal planes of the silicon.

8. The method as claimed in claim 1 , wherein the gate patterns includes a lower gate pattern adjacent to the lower semiconductor pattern and upper gate patterns adjacent to the upper semiconductor pattern, and
wherein the method further comprises forming a horizontal insulator between the lower gate pattern and the lower semiconductor pattern and between the vertical insulator and each of the upper gate patterns,
wherein the horizontal insulator between the lower gate pattern and the lower semiconductor pattern extends onto a top surface and a bottom surface of the lower gate pattern; and
wherein the horizontal insulator between the vertical insulator and each of the upper gate patterns extends onto a top surface and a bottom surface of each of the upper gate patterns.

9. The method as claimed in claim 1 , wherein the vertical insulator includes a protecting layer, a charge storage layer, and a tunnel insulating layer.

10. A method for fabricating a three-dimensional (3D) semiconductor memory device, the method comprising:
forming a mold stack structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate;
forming through-holes penetrating the mold stack structure, the through-holes exposing the substrate;
forming an epitaxial layer in each of the through-holes;
forming a vertical structure in each of the through-holes such that the vertical structure includes a semiconductor pillar;
patterning the mold stack structure to form a trench;
removing the sacrificial layers exposed by the trench to form recess regions;
etching the epitaxial layer exposed by at least a lowermost one of the recess regions to form an epitaxial pattern having a rounded sidewall; and
forming horizontal structures in the recess regions, respectively, such that each of the horizontal structures includes a gate electrode,
wherein at least one of the horizontal structures is in contact with the epitaxial pattern.

11. The method as claimed in claim 10 , wherein forming the epitaxial layer includes:
performing a selective epitaxial growth process using the substrate exposed by the through-holes as a seed; and
wherein a top surface of the epitaxial layer is higher than a top surface of a lowermost one of the horizontal structures.

12. The method as claimed in claim 10 , wherein forming the vertical structure includes:
sequentially forming a protecting layer, a charge storage layer, and a tunnel insulating layer in each of the through-holes; and
forming the semiconductor pillar on the tunnel insulating layer in each of the through-holes.

13. The method as claimed in claim 12 , further comprising selectively removing the protecting layer exposed by the recess regions to expose the charge storage layer after forming the recess regions.

14. The method as claimed in claim 12 , wherein selectively removing the protecting layer and etching the epitaxial layer are performed by a same etching process at a same time.

15. The method as claimed in claim 12 , wherein:
one of the sacrificial layers that contacts the epitaxial layer is formed of a material having an etch selectivity with respect to others of the sacrificial layers; and
removing the sacrificial layers, selectively removing the protecting layer, and etching the epitaxial layer are performed by a same etching process.

16. The method as claimed in claim 10 , wherein a distance between portions of the gate electrode respectively adjacent to both rounded sidewalls of the epitaxial pattern is less than a width of the vertical structure.

17. The method as claimed in claim 10 , wherein:
each vertical structure further includes a charge storage layer and a tunnel insulating layer; and
each of the horizontal structures further includes a blocking insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Dongchul
• Nam Phil Ouk
• Yang Junkyu
• Lee Woong
• Lee Woosung
• Kim Jingyun
• Eom Daehong

Classifications

• H01L29/511

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic