Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9559111-B2
Application number	US-201514790969-A
Country	US
Kind code	B2
Filing date	Jul 2, 2015
Priority date	Sep 11, 2012
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a lower structure including a lower gate pattern and a lower semiconductor pattern penetrating the lower gate pattern, the lower semiconductor pattern being connected to a substrate; and
an upper structure including upper gate patterns stacked on the lower structure, an upper semiconductor pattern penetrating the upper gate patterns, and a vertical insulator between the upper semiconductor pattern and the upper gate patterns, the upper semiconductor pattern being connected to the lower semiconductor pattern,
wherein the lower semiconductor pattern has a rounded sidewall adjacent to the lower gate pattern, and
wherein the lower semiconductor pattern includes an epitaxial pattern.

2. The 3D semiconductor memory device as claimed in claim 1 , wherein a minimum width of the lower semiconductor pattern is less than a lower width of the upper semiconductor pattern.

3. The 3D semiconductor memory device as claimed in claim 1 , wherein the vertical insulator includes a data storage layer.

4. The 3D semiconductor memory device as claimed in claim 1 , wherein the lower semiconductor pattern has a different crystalline structure from the upper semiconductor pattern.

5. The 3D semiconductor memory device as claimed in claim 1 , wherein the lower gate pattern is spaced apart from the rounded sidewall of the lower semiconductor pattern by a first distance, and the upper gate pattern is spaced apart from a sidewall of the upper semiconductor pattern by a second distance greater than the first distance.

6. The 3D semiconductor memory device as claimed in claim 1 , further comprising a horizontal insulator between the lower gate pattern and the lower semiconductor pattern and between the vertical insulator and each of the upper gate patterns,
wherein:
the horizontal insulator between the lower gate pattern and the lower semiconductor pattern extends onto a top surface and a bottom surface of the lower gate pattern; and
the horizontal insulator between the vertical insulator and each of the upper gate patterns extends onto a top surface and a bottom surface of each of the upper gate patterns.

7. The 3D semiconductor memory device as claimed in claim 1 , wherein a maximum width of the lower semiconductor pattern is greater than a maximum width of the upper semiconductor pattern.

8. A three-dimensional (3D) semiconductor memory device, comprising:
a stack structure including insulating layers vertically stacked on a substrate and a lower gate pattern between the insulating layers;
a lower semiconductor pattern penetrating the lower gate pattern and being connected to the substrate, the lower semiconductor pattern including first portions adjacent to the insulating layers and a second portion adjacent to the lower gate pattern;
an upper gate pattern stacked on the insulating layers; and
a semiconductor pillar disposed through the upper gate pattern in a direction substantially vertical with respect to the substrate,
wherein the second portion of the lower semiconductor pattern has a rounded sidewall, and the lower semiconductor pattern includes an epitaxial pattern, and
wherein the rounded sidewall has a first degree of curvature and a sidewall of the semiconductor pillar adjacent to the upper gate pattern has a second degree of curvature, and the first degree is greater than the second degree.

9. The 3D semiconductor memory device as claimed in claim 8 , wherein the second portion of the lower semiconductor pattern has a width less than that of the first portion of the lower semiconductor pattern.

10. The 3D semiconductor memory device as claimed in claim 8 , further comprising a horizontal insulator between the lower gate pattern and the lower semiconductor pattern, the horizontal insulator extending onto a top surface and a bottom surface of the lower gate pattern.

11. A three-dimensional (3D) semiconductor memory device, further comprising:
a stack structure including insulating layers vertically stacked on a substrate and a lower gate pattern between the insulating layers;
a lower semiconductor pattern penetrating the lower gate pattern and being connected to the substrate, the lower semiconductor pattern including first portions adjacent to the insulating layers and a second portion adjacent to the lower gate pattern;
upper gate patterns stacked on the lower gate pattern;
an upper semiconductor pattern penetrating the upper gate patterns and being connected to the lower semiconductor pattern; and
a vertical insulator between the upper semiconductor pattern and the upper gate patterns, wherein the second portion of the lower semiconductor pattern has a rounded sidewall.

12. The 3D semiconductor memory device as claimed in claim 11 , wherein the vertical insulator includes a data storage layer.

13. The 3D semiconductor memory device as claimed in claim 11 , wherein the lower gate pattern is spaced apart from the rounded sidewall of the lower semiconductor pattern by a first distance, and the upper gate pattern is spaced apart from a sidewall of the upper semiconductor pattern by a second distance greater than the first distance.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Dongchul
• Nam Phil Ouk
• Yang Junkyu
• Lee Woong
• Lee Woosung
• Kim Jingyun
• Eom Daehong

Classifications

• H01L29/7926

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10D64/681

  having a compositional variation, e.g. multilayered · CPC title