Three-dimensional integrated circuit structure

Patent metadata

Field	Value
Publication number	US-9899355-B2
Application number	US-201514870006-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Provided is a 3DIC structure including first and second IC chips and connectors. The first IC chip includes a first metallization structure, a first optical active component, and a first photonic interconnection layer. The second IC chip includes a second metallization structure, a second optical active component, and a second photonic interconnection layer. The first and second IC chips are bonded via the first and second photonic interconnection layers. The first optical active component is between the first photonic interconnection layer and the first metallization structure. The first optical active component and the first metallization structure are bonded to each other. The second optical active component is between the second photonic interconnection layer and the second metallization structure. The second optical active component and the second metallization structure are bonded to each other.

First claim

What is claimed is:

1. A 3D integrated circuit structure, comprising:
a first IC chip comprising a first metallization structure, a first optical active component, and a first photonic interconnection layer; and
a second IC chip comprising a second metallization structure, a second optical active component, and a second photonic interconnection layer,
wherein the first IC chip and the second IC chip are bonded via the first photonic interconnection layer and the second photonic interconnection layer,
wherein the first optical active component is located between the first photonic interconnection layer and the first metallization structure, and
wherein the second optical active component is located between the second photonic interconnection layer and the second metallization structure,
wherein the first optical active component and the first metallization structure are bonded by a first hybrid bonding structure, and the second optical active component and the second metallization structure are bonded by a second hybrid bonding structure,
wherein the first hybrid bonding structure comprises:
a first bonding layer of the first metallization structure, comprising a first pad in a first dielectric layer; and
a second bonding layer of the first optical active component, comprising a second pad in a second dielectric layer, wherein the first pad and the second pad are bonded to each other, and the first dielectric layer and the second dielectric layer are bonded to each other,

wherein the second hybrid bonding structure comprises:
a third bonding layer of the second metallization structure, comprising a third pad in a third dielectric layer; and
a fourth bonding layer of the second optical active component, comprising a fourth pad in a fourth dielectric layer, wherein the third pad and the fourth pad are bonded to each other, and the third dielectric layer and the fourth dielectric layer are bonded to each other.

2. The 3D integrated circuit structure according to claim 1 , further comprising:
an encapsulant disposed aside the first IC chip; and
a plurality of connectors being over a bottom surface of the first IC chip and respectively electrically connecting the first IC chip and the second IC chip.

3. The 3D integrated circuit structure according to claim 2 , further comprising:
a first TSV electrically connected with a first connector of the connectors and extending from the bottom surface of the first IC chip to a conductive line layer in the first metallization structure; and
a second TSV electrically connected with a second connector of the connectors and extending from the bottom surface of the first IC chip to the third bonding layer of the second metallization structure,
wherein the first photonic interconnection layer and the second photonic interconnection layer are bonded by dielectric-to-dielectric bonding.

4. The 3D integrated circuit structure according to claim 3 , further comprising a through dielectric via (TDV) electrically connected with a third connector of the connectors and penetrating through the encapsulant from the bottom surface of the first IC chip to the third bonding layer of the second metallization structure.

5. The 3D integrated circuit structure according to claim 2 , further comprising:
a first TSV electrically connected with a first connector of the connectors and extending from the bottom surface of the first IC chip to a conductive line layer in the first metallization structure;
a second TSV electrically connected with a second connector of the connectors and extending from the bottom surface of the first IC chip to the conductive line layer in the first metallization structure;
a first via passing through a first insulating material aside the first optical active component and the first bonding layer and connected with the conductive line layer of the first metallization structure;
a first conductive material in the first photonic interconnection layer and connected with the first via;
a second conductive material in the second photonic interconnection layer and bonded to the first conductive material; and
a second via connected with the second conductive material and passing through the second photonic interconnection layer and a second insulating material aside the second optical active component and connected with the third bonding layer,
wherein the first IC chip and the second IC chip are bonded by hybrid bonding.

6. The 3D integrated circuit structure according to claim 5 , further comprising a TDV electrically connected with a third connector of the connectors and penetrating through the encapsulant from the bottom surface of the first IC chip to the third bonding layer of the second metallization structure.

7. The 3D integrated circuit structure according to claim 2 , further comprising:
a first TSV electrically connected with a first connector of the connectors and extending from a first conductive line layer of the first metallization structure to the bottom surface of the first IC chip;
a second TSV electrically connected with a second connector of the connectors and extending from the first conductive line layer of the first metallization structure to the bottom surface of the first IC chip;
a first via passing through a first insulating material aside the first optical active component and the first bonding layer and connected with a second conductive line layer of the first metallization structure;
a first conductive material in the first photonic interconnection layer and connected with the first via;
a second conductive material in the second photonic interconnection layer and bonded to the first conductive material; and
a second via connected with the second conductive material and passing through a second insulating material aside the second optical active component and the second photonic interconnection layer and connected with the third bonding layer,
wherein the first IC chip and the second IC chip are bonded by hybrid bonding.

8. The 3D integrated circuit structure according to claim 7 , further comprising a through dielectric via (TDV) electrically connected with a third connector of the connectors and penetrating through the encapsulant from the bottom surface of the first IC chip to the third bonding layer of the second metallization structure.

9. The 3D integrated circuit structure according to claim 1 , further comprising:
an encapsulant disposed aside the first IC chip; and
a plurality of connectors being over a bottom surface of the second IC chip and respectively electrically connecting the first IC chip and the second IC chip.

10. The 3D integrated circuit structure according to claim 9 , further comprising:
a first TSV electrically connected with a first connector of the connectors and extending from a conductive line layer of the second metallization structure to the bottom surface of the second IC chip;
a first via passing through a first insulating material aside the first optical active component and connected with the first bonding layer;
a first conductive material in the first photonic interconnection layer and connected with the first via;
a second conductive material in the second photonic interconnection layer and bonded to the first conductive material;
a second via connected with the second conductive material and passing through the second photonic interconnection layer and a second insulating material aside the second optical active component and bonded to the third bonding layer, wherein the first IC chip and the second IC chip are bonded by hybrid bonding; and
a second TSV extending from the conductive line layer in the second metallization structure to the bottom surface of the secon

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yuan Ching Pin
• Yu Chen Hua
• Chen Ming Fa
• Yeh Sung Feng

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/073

  of die-attach connectors · CPC title