Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer

Patent metadata

Field	Value
Publication number	US-9899322-B2
Application number	US-201615257921-A
Country	US
Kind code	B2
Filing date	Sep 7, 2016
Priority date	Aug 28, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a metal gate on the substrate;
a hard mask on the metal gate;
an interlayer dielectric (ILD) layer around the metal gate; and
a patterned metal layer embedded in the ILD layer, wherein the patterned metal layer comprises a step directly on top of the hard mask and an absolute bottom surface of the patterned metal layer is higher than a top surface of the metal gate.

2. The semiconductor device of claim 1 , further comprising a patterned dielectric stack on the patterned metal layer, wherein the patterned dielectric stack comprises silicon nitride and silicon dioxide.

3. The semiconductor device of claim 1 , wherein the step is on part of the hard mask.

4. The semiconductor device of claim 1 , wherein the patterned metal layer comprises TiN.

5. The semiconductor device of claim 1 , further comprising a shallow trench isolation (STI) in the substrate, wherein the patterned metal layer is on the STI.

6. The semiconductor device of claim 5 , wherein the STI is overlaid by the patterned metal layer entirely.

7. The semiconductor device of claim 1 , wherein a top surface of the patterned metal layer is lower than a top surface of the hard mask.

8. The semiconductor device of claim 1 , wherein the patterned metal layer is directly on top of the ILD layer.

9. A semiconductor device, comprising:
a substrate;
a metal gate on the substrate;
a hard mask on the metal gate;
an interlayer dielectric (ILD) layer around the metal gate;
a patterned metal layer embedded in the ILD layer, wherein the patterned metal layer comprises a step directly on top of the hard mask and a bottom surface of the patterned metal layer is higher than a top surface of the metal gate; and
a patterned dielectric stack on the patterned metal layer, wherein the patterned dielectric stack comprises silicon nitride and silicon dioxide.

10. The semiconductor device of claim 9 , wherein the step is on part of the hard mask.

11. The semiconductor device of claim 9 , further comprising a shallow trench isolation (STI) in the substrate, wherein the patterned metal layer is on the STI.

12. The semiconductor device of claim 11 , wherein the STI is overlaid by the patterned metal layer entirely.

13. The semiconductor device of claim 9 , wherein a top surface of the patterned metal layer is lower than a top surface of the hard mask.

14. The semiconductor device of claim 9 , wherein the patterned metal layer is directly on top of the ILD layer.

Assignees

• United Microelectronics Corp

Inventors

• Lin Ching Ling
• Huang Chih Sen
• Hung Ching Wen
• Wu Jia Rong
• Chang Tsung Hung
• Lee Yi Hui
• Chen yi wei

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/4446

  Refractory-metal alloys · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title