Fractional divider using a calibrated digital-to-time converter

Patent metadata

Field	Value
Publication number	US-9897976-B2
Application number	US-201715479499-A
Country	US
Kind code	B2
Filing date	Apr 5, 2017
Priority date	Jun 17, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

First claim

The invention claimed is:

1. An apparatus comprising:
a first control circuit (i) comprising a plurality of capacitances and (ii) configured to generate an output clock signal in response to a divided clock signal, a first feedback signal and a second feedback signal;
a second control circuit configured to generate said first feedback signal and an error signal in response to said divided clock signal and a state signal;
a first feedback circuit configured to generate said state signal in response to said output clock signal; and
a second feedback circuit configured to generate said second feedback signal in response to said error signal, wherein (i) one or more of said capacitances are engaged to add a delay to one or more edges of said output clock signal, (ii) a number of said capacitances engaged is selected to reduce jitter on said output clock signal, and (iii) said capacitances are used each cycle to calibrate said output clock signal.

2. The apparatus according to claim 1 , wherein at least one period of delay is added when said number of said capacitances engaged is a total number of said capacitances available.

3. The apparatus according to claim 1 , wherein a minimal amount of delay is added when said number of said capacitances engaged is zero.

4. The apparatus according to claim 1 , wherein (i) said first feedback signal is used to select said number of said capacitances engaged and (ii) said first feedback signal is calibrated during each period of said output clock signal.

5. The apparatus according to claim 1 , wherein said capacitances comprise a plurality of digitally controlled varactors.

6. The apparatus according to claim 1 , wherein (i) a total number of said capacitances available is 512 and (ii) a 9-bit signal is implemented to select said number of said capacitances engaged.

7. The apparatus according to claim 1 , wherein (i) a total number of said capacitances available is 560 and (ii) a 10-bit signal is implemented to select said number of said capacitances engaged.

8. The apparatus according to claim 1 , wherein (i) said second control circuit is configured to convert said state signal to a phase value, (ii) said phase value and a previous phase value are used to calculate a period value for a clock pulse width and (iii) said period value is used as said first feedback signal.

9. The apparatus according to claim 1 , wherein said second control circuit is configured to generate said error signal in response to a delta-sigma modulation (DSM) overflow.

10. The apparatus according to claim 9 , wherein said error signal is generated by said second control circuit performing a comparison of a current value of said state signal and a previous value of said state signal.

11. The apparatus according to claim 9 , wherein said delta-sigma modulation overflow occurs when said first circuit changes a state.

12. The apparatus according to claim 9 , wherein (i) said second feedback circuit is implemented as a digital-to-analog converter, (ii) said first control circuit is implemented as a digital-to-time converter, (iii) said second feedback is a gain and (iv) said digital-to-analog converter adjusts said gain in response to said error signal and presents said gain to said digital-to-time converter.

13. The apparatus according to claim 12 , wherein said digital-to-time converter uses said gain to calibrate and settle to a value to reduce an amount of said jitter.

14. The apparatus according to claim 1 , wherein said first feedback circuit comprises a measurement circuit configured to perform a cycle-to-cycle comparison of said output clock signal.

15. The apparatus according to claim 14 , wherein (A) said measurement circuit comprises a gated ring oscillator and (B) slow changes in oscillator frequency are rejected by said gated ring oscillator.

16. The apparatus according to claim 1 , wherein said second feedback circuit comprises a digital state machine implementing at least one of (i) a dynamic-element-matching component and (ii) a delta-sigma modulation component.

17. The apparatus according to claim 1 , wherein mismatched capacitances in said first control circuit are linearized using at least one of (i) dynamic-element-matching and (ii) scrambling techniques.

18. A method for reducing jitter on a signal, comprising the steps of:
(A) receiving an input clock signal;
(B) receiving a configuration signal;
(C) generating (i) a divided clock signal and (ii) a control signal;
(D) selecting a number of a plurality of capacitances to engage; and
(E) generating an output clock signal in response to (i) said control signal and (ii) said divided clock signal, wherein (a) a delay is added to one or more edges of said output clock signal by engaging one or more of a plurality of said capacitances, (b) said number of said capacitances engaged is selected to reduce jitter on said output clock signal, and (c) said capacitances are used each cycle to calibrate said output clock signal, wherein (i) a fractional divider circuit based on a calibrated digital-to-time converter is implemented to (a) receive said input clock signal, (b) receive said configuration signal and (c) generate said divided clock signal and (ii) a jitter reduction circuit is implemented to (a) receive said control signal, (b) receive said divided clock signal and (c) generate said output clock signal.

Assignees

• Integrated Device Tech

Inventors

• Gao Song
• Buell Brian
• Blinick Katherine T

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/1009

  Calibration · CPC title

• G04G3/02

  Circuits for deriving low frequency timing pulses from pulses of higher frequency (pulse frequency dividers in general H03K23/00 - H03K29/00) · CPC title