Time to digital converter with successive approximation architecture

Patent metadata

Field	Value
Publication number	US-9285778-B1
Application number	US-201514828728-A
Country	US
Kind code	B1
Filing date	Aug 18, 2015
Priority date	Aug 18, 2015
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A time to digital converter with a successive approximation architecture ( 300 ) and a method thereof is provided. The time to digital converter ( 300 ) includes successive approximation analog to digital converter circuitry ( 310 ) configured for converting the differential voltage established in the digital to analog converter ( 305 ) of the successive approximation analog to digital converter circuitry ( 310 ) to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter ( 300 ) may incorporate a current switching unit ( 340 ′) having a plurality of current switching circuits ( 303 a - 303 n, 304 a - 304 n ) arranged in parallel to increase the precision of digital time output of time to digital converter ( 300 ). The plurality of current switching circuits ( 303 a - 303 n, 304 a - 304 n ) can be selectively enabled to alter the sensitivity of the time to digital converter ( 300 ).

First claim

What is claimed is:

1. A time to digital converter comprising:
a phase-frequency detection circuit having a pair of inputs respectively receiving first and second signals, said phase-frequency detection circuit generating both an up and a down control signal at corresponding outputs thereof, one of said up and down control signals having a pulse width representing a time difference between leading edges of said first and second signals, one relative to the other;
a capacitor digital to analog converter operatively coupled to the outputs of said phase-frequency detection circuit, said capacitor digital to analog converter having a pair of capacitor arrays each redistributing charge in correspondence to said pulse width of a corresponding one of said up and down control signals and sequentially switching selected capacitors of at least one of said pair of capacitor arrays to establish respective voltage output for each of said pair of capacitor arrays;
a successive approximation logic and timing unit coupled to said capacitor digital to analog converter for controlling the sequential switching of said selected capacitors, said successive approximation logic and timing unit including a successive approximation register; and
a comparator unit operatively coupled to said pair of capacitor arrays for comparing voltage outputs thereof and operatively coupled to said successive approximation logic and timing unit, said comparator unit having an output coupled to said successive approximation register, said comparator generating a bit value respectively for each of a plurality of bit conversion states established by said successive approximation logic and timing unit and outputting said bit values to the successive approximation register to form a digital representation of the time difference between leading edges said first and second signals.

2. The time to digital converter as recited in claim 1 , further comprising a current switching unit having a pair of inputs coupled to said outputs of said phase-frequency detection circuit for receiving said up and down control signals and outputs coupled to said capacitor digital to analog converter for establishing said charge redistributed by a corresponding one of said pair of capacitor arrays in correspondence to said pulse width of said corresponding one of said up and down control signals.

3. The time to digital converter as recited in claim 2 , where said current switching unit includes at least one first current switching circuit operatively coupled to said up control signal and at least one second current switching circuit operatively coupled to said down control signal.

4. The time to digital converter as recited in claim 3 , where each of said first and second current switching circuits includes a first transistor and at least one second transistor coupled in series, said first transistor being biased to establish a current switched by said at least one second transistor to establish said charge redistributed by a corresponding one of said pair of capacitor arrays in correspondence to said pulse width of said corresponding one of said up and down control signals.

5. The time to digital converter as recited in claim 4 , where each of said first and second current switching circuits further includes a third transistor coupled between a reference voltage and a drain of said first transistor, said third transistor being switched on to maintain a charge on a parasitic capacitance of said drain of said first transistor when said at least one second transistor is switched off.

6. The time to digital converter as recited in claim 3 , where each of said first and second current switching circuits includes a first transistor and a pair of second transistors coupled in series, said first transistor being biased to establish a current switched by said pair of second transistors to establish said charge redistributed by a corresponding one of said pair of capacitor arrays in correspondence to said pulse width of said corresponding one of said up and down control signals, a source of one of said pair of second transistors being coupled to a drain of said first transistor and a drain of the other of said pair of second transistors being coupled to a source of said first transistor.

7. The time to digital converter as recited in claim 6 , where each of said first and second current switching circuits further includes a third transistor coupled between a reference voltage and said drain of said first transistor, said third transistor being switched on to maintain a charge on a parasitic capacitance of said drain of said first transistor when said pair of second transistors are switched off.

8. The time to digital converter as recited in claim 3 , where said current switching unit includes a plurality of first current switching circuits coupled in parallel relationship and operatively coupled to said up control signal, and a plurality of second current switching circuits coupled in parallel relationship and operatively coupled to said down control signal.

9. The time to digital converter as recited in claim 3 , where said current switching unit includes a selected portion of a plurality of first current switching circuits coupled in parallel relationship and operatively coupled to said up control signal, and a selected portion of a plurality of second current switching circuits coupled in parallel relationship and operatively coupled to said down control signal, said selected portions of said plurality of first and said plurality of second current switching circuits being equal to one another.

10. The time to digital converter as recited in claim 8 , where each of said plurality of first current switching circuits and each of said plurality of second current switching circuits includes a first transistor and at least one second transistor coupled in series, said first transistor being biased to establish a current switched by said at least one second transistor to establish said charge redistributed by a corresponding one of said pair of capacitor arrays in correspondence to said pulse width of said corresponding one of said up and down control signals.

11. The time to digital converter as recited in claim 10 , where each of said plurality of first current switching circuits and each of said plurality of second current switching circuits further includes a third transistor coupled between a reference voltage and a drain of said first transistor, said third transistor being switched on to maintain a charge on a parasitic capacitance of said drain of said first transistor when said at least one second transistor is switched off.

12. The time to digital converter as recited in claim 9 , where each of said selected portion of said plurality of first current switching circuits and each of said selected portion of said plurality of second current switching circuits includes a first transistor and at least one second transistor coupled in series, said first transistor being biased to establish a current switched by said at least one second transistor to establish said charge redistributed by a corresponding one of said pair of capacitor arrays in correspondence to said pulse width of said corresponding one of said up and down control signals.

13. The time to digital converter as recited in claim 12 , where each of said selected portion of said plurality of first current switching circuits and each of said selected portion of said plurality of second current switching circuits further includes a third transistor coupled between a reference voltage and a drain of said first transistor, said third transistor being switched on to maintain a charge on a parasitic

Assignees

• Cadence Design Systems Inc

Inventors

• Evans William P
• Caviglia Anthony
• Naviasky Eric

Classifications

• H03L7/0805

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• H03M1/466

  using switched capacitors · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title