Forwarded clock jitter reduction

Patent metadata

Field	Value
Publication number	US-9319039-B2
Application number	US-201113976877-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

In some embodiments, a differential amplifier with duty cycle correction is provided.

First claim

What is claimed is:

1. A chip, comprising:
a differential amplifier to receive a differential clock; and
an offset compensation circuit coupled to the differential amplifier to adjust offset in the differential clock, the offset compensation circuit to be digitally controlled based on offset in the differential clock, wherein the offset compensation circuit is part of an active high-pass filter circuit.

2. The chip of claim 1 , in which the differential clock is a forwarded clock from another chip.

3. The chip of claim 1 , in which the offset compensation circuit is disposed between the amplifier and electrical contacts for receiving the differential clock from off of the chip.

4. The chip of claim 1 , in which the active high-pass filter circuit implements a continuous time linear equalizer circuit.

5. The chip of claim 1 , comprising a variable offset comparator to receive a low-pass filtered version of an output of the differential amplifier and to generate a digital value representing whether or not a duty cycle of the differential clock is above or below a threshold.

6. The chip of claim 5 , in which the duty cycle threshold is 50%.

7. The chip of claim 1 , comprising a switch to receive a failover clock to be used as an output differential clock.

8. A chip, comprising:
a differential amplifier having an input to receive a differential clock and an output to provide a duty cycle adjusted clock; and
an offset adjustment circuit coupled between the input and output, said offset adjustment circuit including a variable offset comparator (VOC) with self offset correction, a differential offset compensation (DOC) circuit having an output coupled to the input of the differential amplifier, and a control circuit coupled between the VOC and DOC to control output clock duty cycle.

9. The chip of claim 8 , in which the differential clock is a forwarded clock from another chip.

10. The chip of claim 8 , in which the offset compensation circuit is disposed between the amplifier and electrical contacts for receiving the clock from off of the chip.

11. The chip of claim 8 , in which the offset compensation circuit is part of an active filter circuit.

12. The chip of claim 11 , in which the active filter circuit implements a continuous time linear equalizer circuit.

13. The chip of claim 8 , wherein the VOC is to receive a low-pass filtered version of the differential clock to generate a digital value representing whether or not a duty cycle of the clock is above or below a threshold.

14. The chip of claim 13 , in which the duty cycle threshold is 50%.

15. The chip of claim 8 , comprising a switch to receive a failover clock to be used as the differential clock.

Assignees

• Roytman Eduard
• Nagarajan Mahalingam
• Vempada Pradeep R
• Intel Corp

Inventors

• Roytman Eduard
• Nagarajan Mahalingam
• Vempada Pradeep R

Classifications

• H04L25/0274

  Arrangements for ensuring balanced coupling · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H04L25/0296

  Arrangements to ensure DC-balance · CPC title