Integrated semiconductor device and manufacturing method

US9896329B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9896329-B2
Application numberUS-201615208975-A
CountryUS
Kind codeB2
Filing dateJul 13, 2016
Priority dateJul 17, 2015
Publication dateFeb 20, 2018
Grant dateFeb 20, 2018

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to an integrated semiconductor device, comprising a semiconductor substrate; a cavity formed into the semiconductor substrate; a sensor portion of the semiconductor substrate deflectably suspended in the cavity at one side of the cavity via a suspension portion of the semiconductor substrate interconnecting the semiconductor substrate and the sensor portion thereof, wherein an extension of the suspension portion along the side of the cavity is smaller than an extension of said side of the cavity.

First claim

Opening claim text (preview).

What is claimed is: 1. Integrated semiconductor device, comprising: a semiconductor substrate; a cavity formed into the semiconductor substrate; a sensor portion of the semiconductor substrate deflectably suspended in the cavity at one side of the cavity via a suspension portion of the semiconductor substrate interconnecting the semiconductor substrate and the sensor portion thereof, wherein an extension of the suspension portion along the side of the cavity is smaller than an extension of said side of the cavity, wherein the cavity is a Silicon-On-Nothing cavity extending below the sensor portion and having a bottom formed by the semiconductor substrate. 2. The integrated semiconductor device of claim 1 , wherein the sensor portion of the semiconductor substrate is configured for an out-of-plane deflection relative to the semiconductor substrate in response to an out-of-plane excitation applied to the integrated semiconductor device. 3. The integrated semiconductor device of claim 1 , wherein the sensor portion and the suspension portion are continuous portions of the semiconductor substrate. 4. The integrated semiconductor device of claim 1 , wherein the suspension portion is a single bar of semiconductor material integrally interconnecting the semiconductor substrate and the sensor portion thereof. 5. The integrated semiconductor device of claim 1 , wherein the suspension portion is at least partially coated with a stress layer configured to apply an offset tensile stress or strain to the sensor portion of the semiconductor substrate. 6. The integrated semiconductor device of claim 1 , wherein the integrated semiconductor device is an accelerometer and wherein the sensor portion of the semiconductor substrate constitutes a proof mass configured for an out-of-plane movement in response to an out-of-plane acceleration of the integrated semiconductor device. 7. The integrated semiconductor device of claim 1 , further comprising: a frame structure formed into the semiconductor substrate, the frame structure surrounding the sensor portion, wherein the frame structure is suspended in the cavity laterally between an edge of the of the sensor portion and an edge of the cavity, wherein the frame structure and the sensor portion are separated by a first gap, and wherein the frame structure and the edge of the cavity are separated by a second gap. 8. The integrated semiconductor device of claim 7 , wherein the sensor portion is a proof mass and comprises a first plurality of comb tines formed into at least one edge of the proof mass, and wherein the frame structure comprises second plurality of comb tines arranged interleaved with the first plurality of comb tines. 9. The integrated semiconductor device of claim 7 , wherein the sensor portion, the frame structure, and the semiconductor substrate are integrally formed, and wherein the sensor portion and the frame structure are suspended in the cavity via a common single suspension portion of the semiconductor substrate integrally interconnecting the semiconductor substrate, the frame structure, and the sensor portion of the semiconductor substrate. 10. The integrated semiconductor device of claim 1 , wherein the sensor portion comprises, at an end of the sensor portion merging into the suspension portion, a trench extending substantially parallel to an edge of the sensor portion facing the suspension portion of the semiconductor substrate. 11. The integrated semiconductor device of claim 1 , wherein the sensor portion of the semiconductor substrate is a membrane configured for an out-of-plane oscillation in response to an out-of-plane pressure applied to the integrated semiconductor device. 12. Integrated semiconductor device, comprising: a semiconductor substrate; a cavity formed into the semiconductor substrate; a continuous sensor portion of the semiconductor substrate deflectably suspended in the cavity at a single side of the cavity via a continuous single suspension bar of the semiconductor substrate integrally interconnecting the semiconductor substrate and the sensor portion thereof, wherein an extension of the suspension bar along the side of the cavity is smaller than an extension of said side of the cavity; and a continuous frame portion of the semiconductor substrate, the frame portion surrounding the sensor portion of the semiconductor substrate, wherein the frame portion is suspended in the cavity, via the suspension bar, laterally between an edge of the sensor portion and an edge of the cavity, wherein the frame portion and the sensor portion are separated by a first gap, and wherein the frame portion and the edge of the cavity are separated by a second gap. 13. The integrated semiconductor device of claim 12 , wherein the continuous sensor portion of the semiconductor substrate is configured for an out-of-plane deflection relative to the semiconductor substrate in response to an out-of-plane excitation applied to the integrated semiconductor device. 14. The integrated semiconductor device of claim 12 , wherein the continuous suspension portion of the semiconductor substrate is at least partially coated with a stress layer configured to apply an offset tensile stress or strain to the continuous sensor portion of the semiconductor substrate. 15. The integrated semiconductor device of claim 12 , wherein the integrated semiconductor device is an accelerometer and wherein the continuous sensor portion of the semiconductor substrate constitutes a proof mass configured for an out-of-plane movement in response to an out-of-plane acceleration of the integrated semiconductor device. 16. The integrated semiconductor device of claim 12 , wherein the continuous sensor portion of the semiconductor substrate is a proof mass and comprises a first plurality of comb tines formed into at least one edge of the proof mass, and wherein the continuous frame portion of the semiconductor substrate comprises second plurality of comb tines arranged interleaved with the first plurality of comb tines. 17. The integrated semiconductor device of claim 12 , wherein the continuous sensor portion, the continuous frame portion, and the semiconductor substrate are integrally formed, and wherein the continuous sensor portion and the continuous frame portion are suspended in the cavity via the continuous suspension bar integrally interconnecting the semiconductor substrate, the continuous frame portion, and the continuous sensor portion of the semiconductor substrate. 18. The integrated semiconductor device of claim 12 , wherein the continuous sensor portion of the semiconductor substrate comprises, at an end of the continuous sensor portion merging into the continuous suspension bar of the semiconductor substrate, a trench extending substantially parallel to an edge of the continuous sensor portion facing the continuous suspension bar of the semiconductor substrate. 19. The integrated semiconductor device of claim 12 , wherein the continuous sensor portion of the semiconductor substrate is a membrane configured for an out-of-plane oscillation in response to an out-of-plane pressure applied to the integrated semiconductor device.

Assignees

Inventors

Classifications

  • B81C1/0015Primary

    Cantilevers (switches using MEMS H01H1/0036; electrostatic relays using micromechanics H01H59/0009; microelectro-mechanical resonators H03H9/02244) · CPC title

  • Constitution or structural means for improving mechanical properties not provided for in B81B3/007 - B81B3/0075 · CPC title

  • Accelerometers · CPC title

  • Spring holders · CPC title

  • Cantilevers · CPC title

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What does patent US9896329B2 cover?
The present disclosure relates to an integrated semiconductor device, comprising a semiconductor substrate; a cavity formed into the semiconductor substrate; a sensor portion of the semiconductor substrate deflectably suspended in the cavity at one side of the cavity via a suspension portion of the semiconductor substrate interconnecting the semiconductor substrate and the sensor portion thereo…
Who is the assignee on this patent?
Infineon Technologies Dresden Gmbh
What technology area does this patent fall under?
Primary CPC classification B81C1/0015. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Feb 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).