Low drop-out voltage regulator and method of starting same

Patent metadata

Field	Value
Publication number	US-9893607-B1
Application number	US-201715644811-A
Country	US
Kind code	B1
Filing date	Jul 9, 2017
Priority date	Apr 25, 2017
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A low drop-out voltage regulator (LDO) includes an LDO unit, a switch circuit, a charge pump, and an initiation circuit. The switch circuit is coupled to a voltage input terminal and outputs a selected input voltage. The LDO unit receives the selected input voltage from the switch circuit and generates a regulated output voltage. The charge pump is coupled to the LDO unit to receive the regulated output voltage, and generate a control signal that is provided to the switch circuit. The initiation circuit receives the input voltage and generates an initiation voltage that greater than the regulated output voltage. The initiation voltage is provided to the charge pump circuit, along with the regulated output voltage. The initiation voltage drives the charge pump circuit when the regulated output voltage is not large enough to drive the charge pump circuit.

First claim

The invention claimed is:

1. A low drop-out voltage regulator (LDO) for providing a regulated output voltage, the LDO comprising:
an LDO unit having an input terminal and an output terminal for providing the regulated output voltage;
a switch circuit coupled between a voltage input terminal of the LDO and the input terminal of the LDO unit, wherein the switch circuit provides an input voltage to the LDO unit;
a charge pump circuit having an input terminal coupled to the output terminal of the LDO unit and an output terminal coupled to a control terminal of the switch circuit, wherein the charge pump circuit receives the regulated output voltage and provides a switch control signal to the switch circuit; and
an initiation circuit having an input terminal that receives the input voltage and an output terminal coupled to the input terminal of the charge pump circuit, wherein the initiation circuit generates an initiation voltage that is greater than the regulated output voltage to drive the charge pump circuit when the regulated output voltage is not large enough to drive the charge pump circuit.

2. The LDO of claim 1 , wherein the LDO unit comprises:
an LDO amplifier having a first input terminal coupled to a reference voltage, a second input terminal and an output terminal;
an LDO output transistor having a control terminal coupled to the output terminal of the LDO amplifier, a first current electrode coupled to the switch circuit for receiving the input voltage, and a second current electrode that provides the regulated output voltage; and
a feedback circuit coupled between the second current electrode of the LDO output transistor and ground, wherein the feedback circuit provides a feedback voltage to the second input terminal of the LDO amplifier.

3. The LDO of claim 2 , wherein the LDO output transistor is an NMOS transistor.

4. The LDO of claim 1 , wherein the initiation circuit comprises:
an amplifier having a first input terminal coupled to a reference voltage, a second input terminal, and an output terminal;
a first output transistor having a control terminal coupled to the output terminal of the initiation amplifier, a first current electrode coupled to the switch circuit for receiving the input voltage, and a second current electrode coupled to the input terminal of the charge pump circuit; and
a feedback circuit coupled between the second current electrode of the first output transistor and ground, wherein the feedback circuit provides a feedback voltage to the second input terminal of the amplifier.

5. The LDO of claim 4 , wherein the amplifier comprises:
a first amplifier transistor having a source terminal coupled to the switch circuit for receiving the input voltage, a gate terminal, and a drain terminal, wherein the gate and drain terminals of the first amplifier transistor are coupled together;
a second amplifier transistor having a gate terminal coupled to the reference voltage, a drain terminal coupled to the drain terminal of the first amplifier transistor, and a source terminal;
a third amplifier transistor having a gate terminal coupled to the feedback circuit for receiving the feedback voltage, a source terminal coupled to the source terminal of the second amplifier transistor, and a drain terminal;
a first current source coupled between the voltage input terminal of the LDO and the control terminal of the first output transistor;
a diode coupled between the first current source and the drain terminal of the third amplifier transistor; and
a second current source coupled between the source terminals of the second and third amplifier transistors and ground.

6. The LDO of claim 5 , wherein the first amplifier transistor is a PMOS transistor, and the second and third amplifier transistors are NMOS transistors.

7. The LDO of claim 5 , wherein the LDO unit comprises:
a fourth amplifier transistor having a gate terminal coupled to the feedback circuit for receiving the feedback voltage, a source terminal coupled to the source terminals of the second and third amplifier transistors, and a drain terminal;
a fifth amplifier transistor having a gate terminal coupled to the gate terminal of the first amplifier transistor, a source terminal coupled to the source terminal of the first amplifier transistor, and a drain terminal coupled to the drain terminal of the fourth amplifier transistor; and
a second output transistor having a control terminal coupled to a node between the drain terminals of the fourth and fifth amplifier transistors, a first current electrode coupled to the switch circuit for receiving the input voltage, and a second current electrode that provides the regulated output voltage.

8. The LDO of claim 7 , wherein the fourth amplifier transistor is an NMOS transistor, and the fifth amplifier transistor is a PMOS transistor.

9. The LDO of claim 7 , wherein the first and second output transistors are NMOS transistors.

10. The LDO of claim 4 , wherein the feedback circuit comprises first and second series connected resistors, wherein the feedback voltage is provided at a node between the first and second resistors.

11. The LDO of claim 1 , wherein the switch circuit comprises a first switch transistor having first and second current electrodes respectively coupled to the voltage input terminal and the input terminal of the LDO unit, and a gate terminal coupled to the output terminal of the charge pump circuit for receiving the switch control signal.

12. The LDO of claim 11 , wherein the switch circuit further comprises a second switch transistor having a first current electrode coupled to the first current electrode of the first switch transistor, a second current electrode coupled to the second current electrode of the first switch transistor, and a gate terminal coupled to receive the input voltage.

13. The LDO of claim 12 , wherein the first and second switch transistors are NMOS transistors.

14. The LDO of claim 12 , wherein the second switch transistor has a lower threshold voltage than the first switch transistor.

15. The LDO of claim 12 , further comprising a clamp circuit coupled to the LDO input terminal for receiving the input voltage and generating a clamped input voltage, wherein the gate terminal of the second switch transistor is connected to the LDO input terminal by way of the clamp circuit, and the initiation circuit is connected to the LDO input terminal by way of the clamp circuit.

16. A low drop-out voltage regulator (LDO) that receives an input voltage and provides a regulated output voltage, the LDO comprising:
a switch circuit that receives the input voltage and a supply voltage, and outputs a selected one of the input voltage and the supply voltage;
a LDO unit connected to the switch circuit that receives the selected voltage and generates the regulated output voltage;
a charge pump circuit having an input terminal connected to the LDO unit for receiving the regulated output voltage, and an output terminal coupled to the switch circuit for controlling the selection of the one of the input voltage and the supply voltage; and
an initiation circuit coupled to the charge pump circuit, and configured to provide an auxiliary output voltage that is larger than the regulated output voltage to the charge pump circuit, wherein the auxiliary output voltage drives the charge pump circuit to turn on the switch circuit.

17. The LDO of claim 16 , wherein the switch circuit comprises a transistor having a gate terminal coupled to the charge pump circuit, a drain terminal that receives the supply voltage, and a source terminal

Assignees

• Nxp Bv

Inventors

• Wan Mingliang
• Duan Xindong
• Qing Jian

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• H02M1/36 Primary

  Means for starting or stopping converters · CPC title