Low dropout regulator

Patent metadata

Field	Value
Publication number	US-9018924-B2
Application number	US-201213620056-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Sep 14, 2012
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

Aspects are directed to low dropout regulation. In accordance with one or more embodiments, an apparatus includes a charge pump that generates an output using a reference voltage, a low dropout (LDO) regulator circuit, current-limit and a voltage-limit circuit. The LDO circuit includes an amplifier powered by the charge pump and that provides an LDO voltage output. The voltage-limit circuit includes a transistor coupled between a voltage supply line and the LDO regulator circuit and a gate driven by the charge pump. The voltage-limit circuit limits voltage coupled between the voltage supply line and the LDO regulator circuit based upon the output of the charge pump, such as by coupling the voltage at the voltage supply line via source/drain connection of the transistor under low-voltage conditions, and providing a limited voltage to the LDO regulator circuit under high voltage conditions on the voltage supply line.

First claim

What is claimed is:

1. An apparatus comprising:
a reference voltage supply circuit configured and arranged to supply a reference voltage using a voltage supply line subject to fluctuations in voltage;
a charge pump coupled to receive the reference voltage from the reference voltage supply circuit and to generate an output voltage using the reference voltage;
a voltage-limit circuit including a transistor having a drain coupled to the voltage supply line and a gate connected to the output voltage of the charge pump, the voltage-limit circuit being configured and arranged to limit voltage coupled to its source based upon the output of the charge pump;
a first current limit circuit configured and arranged to limit current flowing from the voltage supply line, via the voltage-limit circuit, to a predefined current limit threshold; and
a low dropout (LDO) regulator circuit including an amplifier coupled to and powered by an output voltage at an output of the charge pump, the LDO regulator circuit being configured and arranged to provide an LDO voltage output using a voltage provided via the source of the transistor in the voltage-limit circuit.

2. The apparatus of claim 1 , further including a capacitor connected to a node coupled between the charge pump and the gate of the transistor, and configured and arranged to maintain a voltage level at the gate in response to a spike on the voltage supply line coupled to the gate.

3. The apparatus of claim 1 , wherein the voltage-limit circuit is configured and arranged to limit voltage coupled between the voltage supply line and the LDO regulator circuit based upon the output of the charge pump by
operating as a switch in a closed position to couple the voltage supply line to the LDO regulator circuit in response to a voltage on the voltage supply line being below an operating voltage of the charge pump at which the charge pump outputs a maximum operating voltage level,
operating as a source follower to limit voltage provided to the LDO regulator circuit to a voltage provided via the charge pump, in response to a voltage on the voltage supply line that exceeds the maximum operating voltage level.

4. The apparatus of claim 1 , wherein the voltage-limit circuit is configured and arranged to
operate as a source follower and limit voltage provided to the LDO regulator circuit in response to a voltage on the voltage supply line in excess of a maximum operating output voltage of the charge pump, and
operate as a resistive switch to pass voltage provided to the LDO regulator circuit in response to a voltage on the voltage supply line being less than the maximum operating output voltage of the charge pump.

5. The apparatus of claim 1 , wherein the transistor is an extended drain NMOS transistor having a drain coupled to the voltage supply line and its source coupled to the LDO regulator circuit via the first current limit circuit, the transistor being configured and arranged to
operate as a source follower and limit voltage provided to the LDO regulator circuit in response to a voltage on the voltage supply line in excess of a maximum operating output voltage of the charge pump, and
operate as a resistive switch to pass voltage provided by the voltage supply line to the LDO regulator circuit in response to a voltage on the voltage supply line being less than a maximum operating output voltage of the charge pump.

6. The apparatus of claim 1 , wherein the reference voltage supply circuit includes a bandgap reference voltage circuit configured and arranged to provide the reference voltage as a bandgap reference voltage using the voltage supply line and by shunting current in response to fluctuations on the voltage supply line to maintain the bandgap reference voltage supplied to the charge pump at about a constant level.

7. The apparatus of claim 1 , wherein the transistor has an extended drain connected to the voltage supply line and a source connected to the LDO regulator circuit, and voltage-limit circuit is configured and arranged to
operate as a resistive switch in response to a voltage on the voltage supply line that is less than the voltage output of the charge pump minus a threshold voltage of the transistor, and
operate as a source follower in response to the voltage on the voltage supply line being greater than the value of a maximum operating voltage output of the charge pump minus the threshold voltage of the transistor, and thereby limit the voltage provided to the LDO regulator circuit to the value of the voltage output of the charge pump minus the threshold voltage of the transistor.

8. The apparatus of claim 1 , wherein
the transistor has a drain connected to the voltage supply line and a source connected to the LDO regulator circuit, and
the transistor includes a built-in diode having its anode coupled to the source and a cathode coupled to the drain.

9. The apparatus of claim 1 , further including a comparator circuit configured and arranged to switch the LDO regulator circuit between ON and OFF states based upon a voltage provided by the charge pump being greater than a predetermined low threshold voltage at which the LDO regulator circuit can operate.

10. The apparatus of claim 9 , wherein the comparator circuit is configured and arranged to switch the LDO regulator circuit to the ON state by, in response to the voltage provided by the voltage supply line being greater than the predetermined low threshold voltage, starting a debounce delay timer and providing a signal to the charge pump and LDO regulator circuit to switch the LDO regulator circuit to an on state after a delay period based on the debounce delay timer.

11. The apparatus of claim 1 , wherein the LDO regulator circuit includes a second transistor having a drain coupled to a voltage passed via the voltage and a plurality of current limit circuits including the first current limit circuit, a source coupled to a ground circuit via at least one resistor, and a gate coupled to the output of the amplifier.

12. The apparatus of claim 11 , further including a second current limit circuit, of the plurality of current limit circuits, coupled between the voltage-limit circuit and the drain of the second transistor, and a replica bias circuit including a third transistor coupled in parallel with the second transistor between the second current limit circuit and the ground circuit.

13. The apparatus of claim 1 , further including an external power supply interface coupled to the voltage supply line and configured and arranged to interface with at least one of: a universal serial bus (USB) based interface, a DisplayPort-based interface and a high-definition multimedia interface (HDMI).

14. An apparatus comprising:
an external power interface configured and arranged to interface with an external power source;
a low dropout (LDO) regulator;
a charge pump circuit configured and arranged to generate a voltage output;
a voltage-limit circuit including a transistor having a source, drain and gate, the drain being coupled to the external power interface, the gate being coupled to receive the charge pump voltage output, the voltage-limit circuit being configured and arranged to limit voltage coupled from the drain to the source, based upon the charge pump voltage output; and
a current limit circuit configured and arranged to limit current flowing on a path, from the source to an output of the LDO regulator, to a transient current limit level lower than a predefined current limit threshold of the external power interface.

15. The circuit of claim 14 , wherein the LDO regulator is configured and arranged to operate

Assignees

• Vemula Madan Mohan Reddy
• Nxp Bv

Inventors

• Vemula Madan Mohan Reddy

Classifications

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title