Bond structures and the methods of forming the same

Patent metadata

Field	Value
Publication number	US-9893028-B2
Application number	US-201514980044-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

First claim

What is claimed is:

1. A method comprising:
forming a first conductive feature and a second conductive feature;
forming a metal pad over and electrically connected to the first conductive feature;
forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the passivation layer;
depositing a first dielectric layer covering the metal pad and the passivation layer;
forming a first bond pad through plating over the first dielectric layer, wherein the first bond pad is electrically coupled to the second conductive feature; and
depositing a second dielectric layer, wherein the second dielectric layer encircles the first bond pad, and the forming the second dielectric layer comprises:
depositing a dielectric barrier layer contacting a top surface and sidewalls of the first bond pad;
depositing an additional dielectric layer over the dielectric barrier layer; and
performing a planarization to remove excess portions of the dielectric barrier layer and the additional dielectric layer higher than the first bond pad.

2. The method of claim 1 , wherein the first bond pad and the second dielectric layer are in a first package component, and the method further comprises bonding the first bond pad and the second dielectric layer with a second package component through hybrid bonding.

3. The method of claim 2 , wherein the first bond pad and the second dielectric layer are in physical contact with an additional bond pad and an additional dielectric layer, respectively, in the second package component.

4. The method of claim 1 further comprising performing a planarization on the second dielectric layer and the first bond pad, wherein at a time after the first bond pad is formed, the top surface of the metal pad is not connected to conductive features.

5. The method of claim 1 further comprising forming a via in the first dielectric layer, wherein the via physically connects the second conductive feature to the first bond pad.

6. The method of claim 1 further comprising forming a second bond pad simultaneously as the first bond pad, wherein the second bond pad is a dummy pad.

7. A method comprising:
forming a first metal feature and a second metal feature;
forming a metal pad over and contacting the first metal feature;
forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the passivation layer;
forming a first dielectric layer to cover the top surface of the metal pad and the passivation layer;
forming a via penetrating through the first dielectric layer and the passivation layer to contact the second metal feature;
forming a first bond pad and a second bond pad simultaneously, with the second bond pad being over and contacting the via;
forming a second dielectric layer to embed the first bond pad and the second bond pad; and
planarizing a top surface of the second dielectric layer to level the top surface of the second dielectric layer with top surfaces of the first bond pad and the second bond pad.

8. The method of claim 7 , wherein the first bond pad is electrically floating.

9. The method of claim 7 further comprising, before the forming the second dielectric layer, forming a dielectric barrier layer on sidewalls and top surfaces of the first bond pad and the second bond pad.

10. The method of claim 7 , wherein the first bond pad is physically isolated from all other conductive features in a respective chip.

11. The method of claim 7 , wherein after the planarizing, an entirety of the top surface of the metal pad is in contact with dielectric materials.

12. The method of claim 11 , wherein after the planarizing, all sidewalls of the metal pad are in contact with dielectric materials.

13. The method of claim 7 , wherein the forming the via and the forming the second bond pad are performed in separate single damascene processes.

14. The method of claim 7 further comprising probing by contacting a probe needle to the top surface of the metal pad.

15. The method of claim 7 further comprising bond the first bond pad and the second bond pad to bond pads of a package component, with the first bond pad and the second bond pad being in physical contact with the bond pads in the package component.

16. The method of claim 7 , wherein the first bond pad overlaps the metal pad, and the first bond pad is a dummy pad.

17. A method comprising:
forming a first conductive pad and a second conductive pad at a same level, wherein the first conductive pad is electrically connected to the second conductive pad through a conductive line;
forming a metal pad over and contacting the first conductive pad;
probing the metal pad;
depositing a first dielectric layer covering the metal pad;
forming a dielectric etch stop layer over the first dielectric layer;
forming a second dielectric layer over the dielectric etch stop layer;
forming a first bond pad in the second dielectric layer, wherein the first bond pad overlaps a portion of the first dielectric layer, and is a dummy bond pad; and
forming a second bond pad penetrating through the second dielectric layer, the dielectric etch stop layer, and the first dielectric layer to contact the second conductive pad.

18. The method of claim 17 further comprising forming a passivation layer covering edge portions of the metal pad, with the probing performed through an opening in the passivation layer, and the first dielectric layer covers the passivation layer.

19. The method of claim 17 , wherein the first bond pad and the second dielectric layer are in a first package component, and the method further comprises bonding the first bond pad and the second dielectric layer with a second package component through hybrid bonding.

20. The method of claim 19 , wherein at a time the bonding is performed, an entire top surface of the metal pad is in contact with dielectric materials.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen Hua
• Chiou Wen Chih
• Chen Ming Fa
• Chen Yi Hsiu

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title