Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area

Patent metadata

Field	Value
Publication number	US-9646901-B2
Application number	US-201615219254-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Mar 31, 2008
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor chip including a main surface, and a pad formed over the main surface;
a first insulating layer formed over the main surface of the semiconductor chip;
a wiring formed over the first insulating layer; and
a bump electrode formed on a part of the wiring,
wherein the pad is located closer than the bump electrode to a peripheral portion of the semiconductor chip,
wherein a probe mark is formed in a first area of a surface of the pad,
wherein the first insulating layer has an opening,
wherein a second area of the surface of the pad is exposed from the opening of the first insulating layer,
wherein the first area is located closer than the second area to a central portion of the semiconductor chip,
wherein the wiring is connected with the pad in the second area but not in the first area, and
wherein the wiring is led from the second area to the central portion of the semiconductor chip such that the wiring does not overlap with the probe mark in a plan view.

2. The semiconductor device according to claim 1 ,
wherein the first area of the surface of the pad is covered with the first insulating layer.

3. The semiconductor device according to claim 1 ,
wherein a second insulating layer is formed over the main surface,
wherein the second insulating layer has an opening,
wherein the surface of the pad is exposed from the opening of the second insulating layer, and
wherein the first insulating layer is formed on the second insulating layer.

4. The semiconductor device according to claim 1 ,
wherein a third insulating layer is formed on the first insulating layer,
wherein the third insulating layer has an opening,
wherein the part of the wiring is exposed from the opening of the third insulating layer.

5. The semiconductor device according to claim 4 ,
wherein a portion of the bump electrode is located inside the opening of the third insulating layer.

6. The semiconductor device according to claim 1 ,
wherein the wiring is connected with the pad via a seed layer.

7. The semiconductor device according to claim 6 ,
wherein the seed layer is extended to a surface of the first insulating layer,
wherein the seed layer is connected with the pad in the second area but not in the first area, and
wherein the wiring is formed on the first insulating layer via the seed layer.

8. The semiconductor device according to claim 1 ,
wherein the probe mark is a damage mark formed by contacting a probe pin with the surface of the pad in a probe test.

9. A semiconductor device, comprising:
a semiconductor chip including a main surface, and a pad formed over the main surface;
a first insulating layer formed over the main surface of the semiconductor chip;
a wiring formed over the first insulating layer; and
a bump electrode formed on a part of the wiring,
wherein the pad is located closer than the bump electrode to a peripheral portion of the semiconductor chip,
wherein a probe mark is formed in a first area of a surface of the pad,
wherein the first insulating layer has an opening,
wherein a second area of the surface of the pad is exposed from the opening of the first insulating layer,
wherein the first area is located closer than the second area to a central portion of the semiconductor chip,
wherein the wiring is connected with the pad in the second area but not in the first area, and
wherein, in plan view, the wiring is led from the second area in a direction away from the first area.

10. The semiconductor device according to claim 9 ,
wherein the first area of the surface of the pad is covered with the first insulating layer.

11. The semiconductor device according to claim 9 ,
wherein a second insulating layer is formed over the main surface,
wherein the second insulating layer has an opening,
wherein the surface of the pad is exposed from the opening of the second insulating layer, and
wherein the first insulating layer is formed on the second insulating layer.

12. The semiconductor device according to claim 9 ,
wherein a third insulating layer is formed on the first insulating layer,
wherein the third insulating layer has an opening,
wherein the part of the wiring is exposed from the opening of the third insulating layer.

13. The semiconductor device according to claim 12 ,
wherein a portion of the bump electrode is located inside the opening of the third insulating layer.

14. The semiconductor device according to claim 9 ,
wherein the wiring is connected with the pad via a seed layer.

15. The semiconductor device according to claim 14 ,
wherein the seed layer is extended to a surface of the first insulating layer,
wherein the seed layer is connected with the pad in the second area but not in the first area, and
wherein the wiring is formed on the first insulating layer via the seed layer.

16. The semiconductor device according to claim 9 ,
wherein the probe mark is a damage mark formed by contacting a probe pin with the surface of the pad in a probe test.

Assignees

• Renesas Electronics Corp

Inventors

• Akiba Toshihiko
• Yasumura Bunji
• Sato Masanao
• Abe Hiromi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07554

  changes in dispositions · CPC title