FinFET and method of forming fin of the FinFET

Patent metadata

Field	Value
Publication number	US-9892977-B2
Application number	US-201615270502-A
Country	US
Kind code	B2
Filing date	Sep 20, 2016
Priority date	Nov 18, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.

First claim

What is claimed is:

1. A method of generating a fin of a FinFET, comprising:
depositing a first hard mask layer on or above a first dummy gate and a second dummy gate;
generating first spacers on the first dummy gate and second spacers on the second dummy gate by etching the first hard mask layer;
removing only the first spacers of the first and second spacers;
after removing the first spacers, depositing a second hard mask layer on or above the first dummy gate and the second spacers;
generating third spacers on the first dummy gate and fourth spacers on the second dummy gate by etching the second hard mask layer;
removing the first dummy gate and the second dummy gate; and
generating first fins using the third spacers and generating second fins using the second spacers and the fourth spacers.

2. The method of claim 1 , wherein a line width of the second fins is wider than a line width of the first fins.

3. The method of claim 1 , wherein the first fins and the second fins are generated on a same wafer.

4. The method of claim 1 , wherein the removing only the first spacers includes:
forming a blocking mask surrounding the second dummy gate including the second spacers;
exposing the first dummy gate by removing the first spacers; and
removing the blocking mask.

5. The method of claim 4 , wherein the blocking mask is formed of at least one of a photo-resist, SiO 2 , and anti-reflection coating (ARC).

6. The method of claim 1 , wherein the first and second fins are formed of at least one of silicon and a III-V compound semiconductor.

7. The method of claim 1 , wherein the first hard mask layer and the second hard mask layer are formed using at least one of silicon nitride (Si 3 N 4 ) and photo-resist.

8. The method of claim 1 , wherein the first dummy gate and the second dummy gate are formed by etching at least one of a polysilicon layer and a spin on hardmask (SOH) layer.

9. The method of claim 1 , wherein the first fins and the second fins are used as a channel of one of an nMOSFET and a pMOSFET, respectively.

10. The method of claim 1 , wherein the first fins form an nMOSFET channel, and the second fins form a pMOSFET channel.

11. The method of claim 1 , further comprising:
removing only the third spacers;
after removing the third spacers, depositing a third hard mask layer on or above the first dummy gate and the fourth spacer;
generating fifth spacers of the first dummy gate and sixth spacers of the second dummy gate by etching the third hard mask layer; and
generating first fins using the fifth spacer and generating second fins using the second spacer, the fourth spacer, and the sixth spacer.

12. The method of claim 1 , wherein the fourth spacers are formed on the second spacers.

13. The method of claim 1 , wherein the fourth spacers contact the second spacers.

14. A FinFET generated according to the method of generating a fin of a FinFET of claim 1 .

15. A method of generating a fin of a FinFET, comprising:
generating a first dummy gate on a first region of a semiconductor substrate and a second dummy gate on a second region of the semiconductor substrate;
depositing a first hard mask layer on or above the first dummy gate and the second dummy gate;
generating first spacers on the first dummy gate and second spacers on the second dummy gate by etching the first hard mask layer;
removing the first spacers on the first dummy gate;
depositing a second hard mask layer on or above the first dummy gate, the second dummy gate and the second spacers;
generating third spacers on the first dummy gate and fourth spacers on the second dummy gate by etching the second hard mask layer;
removing the first dummy gate and the second dummy gate; and
generating first fins on the first region using the third spacers and generating second fins on the second region using the second spacers and the fourth spacers.

16. The method of claim 15 , wherein removing the first spacers comprises removing only the first spacers of the first and second spacers.

17. The method of claim 15 , wherein the fourth spacers are formed on the second spacers.

18. The method of claim 15 , wherein the fourth spacers contact the second spacers.

Assignees

• Samsung Electronics Co Ltd
• Samsing Electronics Co Ltd

Inventors

• Pae Sang Woo
• Sagong Hyun Chul
• Kim Jin Ju
• Park June Kyun

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title