Calibration for echo cancellation in a full duplex communication system

Patent metadata

Field	Value
Publication number	US-9887733-B2
Application number	US-201715582371-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Sep 12, 2014
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.

First claim

What is claimed is:

1. A device for full duplex communication over a channel, comprising:
a driver circuit configured to generate a reference signal;
a replica driver circuit configured to generate a calibration signal; and
a calibration circuit coupled to the driver circuit and the replica driver circuit and configured to:
determine a first reference voltage,
adjust an amplitude of the calibration signal linearly,
record a first amplitude value and a second amplitude value of the amplitude of the calibration signal responsive to determining that a first difference between the amplitude of the calibration signal and an amplitude of the reference signal is equal to the first reference voltage, and
determine a calibration amplitude by averaging the first amplitude and the second amplitude values.

2. The device of claim 1 , wherein the calibration module circuit is further configured to:
determine a second reference voltage,
adjust a transition time of the calibration signal linearly,
record a first transition time value and a second transition time value of the calibration signal responsive to determining that a second difference between the amplitude of the calibration signal and the amplitude of the reference signal is equal to the second reference voltage, and
determine a calibration transition time by averaging the first transition time and the second transition time.

3. The device of claim 2 , wherein the calibration circuit comprises a digital-to-analog converter configured to generate the first reference voltage and the second reference voltage, and a comparator circuit configured to compare the difference of the calibration signal and the reference signal to the first reference voltage or the second reference voltage.

4. The device of claim 1 , wherein the calibration circuit determines that the first difference is equal to the first reference voltage responsive to detecting that a pattern of alternating zeros and ones in the first difference disappears.

5. The device of claim 2 , wherein the calibration circuit determines that the second difference is equal to the second reference voltage responsive to detecting that a pattern of alternating zeros and ones in the second difference disappears.

Assignees

• Lattice Semiconductor Corp

Inventors

• Zhou Kai
• Tahk Shinje
• Lei Kai
• Wu Qiming
• Ahn Gijung
• Kim Min Kyu
• Song Fei
• Luo Kexin

Classifications

• H04L5/0091

  Signalling for the administration of the divided path, e.g. signalling of configuration information · CPC title

• H04B3/232 Primary

  using phase shift, phase roll or frequency offset correction · CPC title

• H04L5/14

  Two-way operation using the same type of signal, i.e. duplex · CPC title

• H04M9/082

  using echo cancellers (echo cancellers per se H04B3/23) · CPC title

• H04B1/525

  with means for reducing leakage of transmitter signal into the receiver · CPC title