Selective nitride outgassing process for MEMS cavity pressure control

Patent metadata

Field	Value
Publication number	US-9884758-B2
Application number	US-201615182754-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Jan 15, 2016
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.

First claim

What is claimed is:

1. A method for manufacturing a micro-electromechanical systems (MEMS) package, the method comprising:
forming an outgassing element within a passivation layer over a CMOS substrate;
forming an outgassing resistive layer to cover the outgassing element;
removing the outgassing resistive layer from over the outgassing element; and
bonding a MEMS substrate to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity, wherein after removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity during or after the bonding to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.

2. The method of claim 1 , wherein outgassing resistive layer comprises silicon nitride.

3. The method of claim 1 , wherein the outgassing element is formed by depositing and patterning a high density plasma oxide layer within a trench of the passivation layer, wherein the outgassing element is formed to have an upper surface aligned with that of a hard mask overlying the passivation layer.

4. The method of claim 1 , further comprising:
forming a plurality of semiconductor devices within a substrate;
forming a plurality of metal interconnect layers including metal wire layers and vias within a dielectric structure comprising a plurality of inter-level dielectric layers over the substrate; and
forming the passivation layer over the plurality of metal interconnect layers and the inter-level dielectric layer.

5. The method of claim 4 , further comprising:
performing a second patterning process to the passivation layer and the outgassing resistive layer to form a plurality of bonding trenches through the outgassing resistive layer and the passivation layer, while the outgassing element is protected by the outgassing resistive layer;
wherein the plurality of bonding trenches are formed to expose a top metal layer of the plurality of metal interconnect layers, which is used as a first bonding metal layer for bonding the MEMS substrate and the CMOS substrate.

6. The method of claim 5 , wherein a second bonding metal layer is formed on a protrusion extending outward from the MEMS substrate prior to removing the outgassing resistive layer.

7. A method for manufacturing a micro-electromechanical systems (MEMS) package, the method comprising:
forming an outgassing element at a front side of a CMOS substrate;
forming an outgassing resistive layer to cover the outgassing element;
performing a thermal process to the CMOS substrate;
removing the outgassing resistive layer;
bonding a MEMS substrate to the CMOS substrate to enclose a first MEMS device within a first hermetically sealed cavity having a first pressure and a second MEMS device within a second hermetically sealed cavity having a second pressure; and

wherein after removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity during or after the bonding to increase the second pressure of the second cavity.

8. The method of claim 7 , wherein the outgassing resistive layer comprises silicon nitride.

9. The method of claim 7 , wherein the outgassing element is formed by depositing and patterning a high density plasma oxide layer.

10. The method of claim 7 , wherein the CMOS substrate is formed and patterned by a process comprising:
forming a plurality of semiconductor devices within a semiconductor substrate;
forming a plurality of metal interconnect layers including metal wire layers and vias within a dielectric structure comprising a plurality of inter-level dielectric layers over the semiconductor substrate;
forming a passivation layer over the inter-level dielectric layer;
performing a first patterning process to the passivation layer to form a trench within an upper surface of the passivation layer, wherein the trench comprises the outgassing element in the trench;
forming the outgassing resistive layer to cover the outgassing element;
performing the second patterning process to the passivation layer;
performing the thermal process to releases a second gas from the passivation layer; and
removing the outgassing resistive layer.

11. The method of claim 10 , wherein the passivation layer is patterned by the first patterning process using a hard mask layer, wherein the outgassing element is formed to have an upper surface aligned with an upper surface of the hard mask layer.

12. The method of claim 10 , wherein the second patterning process comprises patterning the passivation layer and the outgassing resistive layer to form a plurality of bonding trenches through the outgassing resistive layer and the passivation layer, while the outgassing element is protected by the outgassing resistive layer.

13. The method of claim 12 , wherein the plurality of bonding trenches are formed to expose a top metal layer of the plurality of metal interconnect layers, which is used as a first bonding metal layer for bonding the MEMS substrate and the CMOS substrate.

14. The method of claim 7 , wherein the MEMS substrate is formed by a process comprising:
forming a first recess and a second recess from a front side of a capping substrate,
bonding a MEMS layer to the front side of the capping substrate; and

patterning the MEMS layer to form the first MEMS device and the second MEMS device;
wherein the first recess is located at a first position in communication with the first MEMS device and configured as a part of the first cavity, and the second recess is located at a second position in communication with the second MEMS device and configured as a part of the second cavity.

15. A method for manufacturing a micro-electromechanical systems (MEMS) package, the method comprising:
forming a passivation layer over a semiconductor substrate to form a CMOS substrate;
forming an outgassing element within the passivation layer;
bonding a MEMS substrate to the CMOS substrate and enclosing a first MEMS device hermetically sealed within a first cavity having a first pressure and a second MEMS device hermetically sealed within a second cavity having a second pressure; and
wherein the outgassing element is exposed to the second cavity, and is configured to release a gas into the second cavity to increase the second pressure of the second cavity to be greater than the first pressure of the first cavity during or after bonding the MEMS substrate to the CMOS substrate;
wherein the outgassing element is formed by patterning to form a trench into the passivation layer using a hard mask layer, depositing an outgassing layer within the trench and over the passivation layer, and removing the outgassing layer from an upper surface of the hard mask layer to form the outgassing element coplanar with the hard mask layer.

16. The method of claim 15 , wherein the outgassing element is formed using a high density plasma oxide.

17. The method of claim 15 ,
wherein the CMOS substrate and the MEMS substrate are bonded through a top metal layer of the CMOS substrate and a conductive bonding pad of the MEMS substrate;
wherein the top metal layer is formed between the passivation layer and the semiconductor substrate.

18. The method of claim 17 , wherein:
wherein the MEMS substrate and the conductive bonding pad are formed to extend through the passivation layer to contact the top metal layer at a bonding interface.

19. The method of claim 15 , further comprising:
forming a first recess and

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Shyh Wei
• Hsu Hsi Cheng
• Chen Hsin Yu
• Chiang Ji Hong
• Weng Jui Chun
• Wu wei ding
• Wu Yu Jui
• Hu Ching Hsiang
• Chen Ming Tsung

Classifications

• B81C2203/0118

  Bonding a wafer on the substrate, i.e. where the cap consists of another wafer · CPC title

• B81B7/0038

  using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters · CPC title

• B81B2207/012

  the micromechanical device and the control or processing electronics being separate parts in the same package · CPC title

• B81C1/00285 Primary

  using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters · CPC title

• B81C2203/0792

  Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title