Interface unit for direct memory access utilizing identifiers

Patent metadata

Field	Value
Publication number	US-9880955-B2
Application number	US-201514688427-A
Country	US
Kind code	B2
Filing date	Apr 16, 2015
Priority date	Apr 17, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

An interface unit is provided for the arrangement between a bus system, to which a processor unit and a data memory are connectable, and a data transporting unit, in particular a network processor, are described. The interface unit carries out a direct memory access to the data memory as a function of an identifier (chid) previously agreed upon between an application and the data transporting unit.

First claim

What is claimed is:

1. An interface unit for arrangement between a bus system and a data transporting unit, a processor unit and a data memory being connectable to the bus system, wherein the interface unit carries out a direct memory access to the data memory as a function of an identifier previously agreed upon between an application running on the processor unit and the data transporting unit, the interface unit comprising:
an arrangement for sending a data segment from the data memory to the data transporting unit; and
an arrangement for ascertaining, from a descriptor of an input descriptor pool, a memory area address of the data segment in the data memory and the agreed upon identifier, wherein:
the interface unit reads the data segment from the data memory with the aid of the direct memory access,
the data segment, including an associated header, is provided to the data transporting unit, and
the header includes the agreed upon identifier,

wherein:
the data segment is part of a data block, and
the descriptor of the input descriptor pool contains a first piece of information which determines a position of the data segment in the data block, and contains a second piece of information which indicates a sending of the data segment.

2. The interface unit as recited in claim 1 , further comprising:
in order to receive at least one of the data segment and the data block from the data transporting unit in the data memory, an arrangement for writing into a descriptor of an output descriptor pool the agreed upon identifier and a third piece of information which determines the position of the data segment in the data block.

3. The interface unit as recited in claim 2 , further comprising:
an arrangement for writing the data segment into the data memory with the aid of a direct memory access; and
an arrangement for storing, after writing the data segment, a piece of information in the associated descriptor that indicates a write access carried out to the data memory.

4. The interface unit as recited in claim 2 , further comprising:
an arrangement for accessing the bus system as a bus master for the direct memory access to the data memory; and
an arrangement for accessing the bus system as a bus slave for writing and reading accesses to at least one of the input descriptor pool and the output descriptor pool.

5. A communication unit, comprising:
a data transporting unit;
an interface unit for arrangement between a bus system and the data transporting unit, a processor unit and a data memory being connectable to the bus system, wherein the interface unit carries out a direct memory access to the data memory as a function of an identifier previously agreed upon between an application running on the processor unit and the data transporting unit, the interface unit including:
an arrangement for sending a data segment from the data memory to the data transporting unit; and
an arrangement for ascertaining, from a descriptor of an input descriptor pool, a memory area address of the data segment in the data memory and the agreed upon identifier, wherein:
the interface unit reads the data segment from the data memory with the aid of the direct memory access,
the data segment, including an associated header, is provided to the data transporting unit, and
the header includes the agreed upon identifier,

wherein:
the data segment is part of a data block, and
the descriptor of the input descriptor pool contains a first piece of information which determines a position of the data segment in the data block, and contains a second piece of information which indicates a sending of the data segment; and

further communication interfaces connected to the data transporting unit and assigned to at least one of different network types and different subnetworks.

6. A method for operating an interface unit arranged between a bus system and a data transporting unit, a processor unit and a data memory being connectable to the bus system, wherein the interface unit carries out a direct memory access to the data memory as a function of an identifier previously agreed upon between an application running on the processor unit and the data transporting unit, wherein the interface unit has an input descriptor pool,
wherein for sending a data segment from the data memory to the data transporting unit, a memory area address of the data segment in the data memory and the agreed upon identifier are written into a descriptor of the input descriptor pool by the application, and wherein the data segment is part of a data block, and the descriptor contains a first piece of information which determines a position of the data segment in the data block, and contains a second piece of information which indicates a sending of the data segment.

7. The method as recited in claim 6 , wherein the application accesses the bus system as a bus master via the processor unit for at least one of a read access and a write access to the input descriptor pool.

8. A non-transitory computer program product, for an interface unit, wherein the computer program product is designed to carry out a method for operating an interface unit arranged between a bus system and a data transporting unit, a processor unit and a data memory being connectable to the bus system, wherein the interface unit carries out a direct memory access to data memory as a function of an identifier previously agreed upon between an application running on the processor unit and the data transporting unit, wherein the interface unit has an input descriptor pool, and wherein for sending a data segment from the data memory to the data transporting unit, a memory area address of the data segment in the data memory and the agreed upon identifier are written into a descriptor of the input descriptor pool by the application, and wherein the data segment is part of a data block, and the descriptor contains a first piece of information which determines a position of the data segment in the data block, and contains a second piece of information which indicates a sending of the data segment.

9. A non-transitory memory unit on which a computer program product is stored, the computer program product being for an interface unit, wherein the computer program product is designed to carry out a method for operating an interface unit arranged between a bus system and a data transporting unit, a processor unit and a data memory being connectable to the bus system, wherein the interface unit carries out a direct memory access to data memory as a function of an identifier previously agreed upon between an application running on the processor unit and the data transporting unit, wherein the interface unit has an input descriptor pool, and wherein for sending a data segment from the data memory to the data transporting unit, a memory area address of the data segment in the data memory and the agreed upon identifier are written into a descriptor of the input descriptor pool by the application, and wherein the data segment is part of a data block, and the descriptor contains a first piece of information which determines a position of the data segment in the data block, and contains a second piece of information which indicates a sending of the data segment.

10. The interface unit as recited in claim 1 , wherein the data transporting unit includes a network processor.

11. The communication unit as recited in claim 5 , wherein the communication unit includes one of a gateway unit and a personal computer.

12. The communication unit as recited in claim 5 , wherein the different network types includes at least two of CAN, FlexRay, and Ethernet.

13. The non-transit

Assignees

• Bosch Gmbh Robert

Inventors

• Brune Andreas
• Pohl Christopher

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/34 Primary

  with priority control · CPC title