Memory control unit and data storage device including the same

Patent metadata

Field	Value
Publication number	US-9652403-B2
Application number	US-201414483990-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Apr 23, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A data storage device includes a storage memory device, a control unit suitable for generating a descriptor, which describes a work for controlling the storage memory device, and storing the descriptor in a working memory, and a memory control unit suitable for generating control signals for the storage memory device by fetching an instruction set from an instruction memory based on the descriptor.

First claim

What is claimed is:

1. A data storage device comprising:
a nonvolatile memory device;
a control unit suitable for generating a descriptor and storing the descriptor in a working memory, wherein the descriptor describes a work for controlling the nonvolatile memory device and includes an address of an instruction set stored in an instruction memory; and
a memory control unit suitable for reading the descriptor from the working memory, fetching the instruction set from the instruction memory based on the address of the instruction set included in the descriptor, adding a descriptor parameter extracted from the descriptor to the fetched instruction set, generating control signals based on the fetched instruction set in which the descriptor parameter is added, and providing the control signals to the nonvolatile memory device,
wherein the instruction set is a set of control signals that are listed in an order of a control procedure of the nonvolatile memory device in order to control the nonvolatile memory device.

2. The data storage device according to claim 1 , wherein the memory control unit comprises:
a descriptor processing block suitable for extracting flail the descriptor parameter corresponding to the fetched instruction set from the descriptor and adding the extracted descriptor parameter to the fetched instruction set; and
a signal generation block suitable for generating the control signals based on the instruction set and the descriptor parameter.

3. The data storage device according to claim 2 , wherein the descriptor processing block comprises:
a direct memory access (DMA) block suitable for reading the descriptor and data from the working memory;
a descriptor fetch block suitable for controlling the DMA block to read the descriptor;
an instruction fetch block suitable for fetching the instruction set based on the address of the instruction set included in the descriptor, extracting the descriptor parameter from the descriptor, and adding the extracted descriptor parameter to the fetched instruction set; and
an instruction push block suitable for providing the fetched instruction set and the descriptor parameter that is added to the fetched instruction set to the signal generation block, and processing the read data to be provided to the nonvolatile memory device, or data read from the nonvolatile memory device.

4. The data storage device according to claim 3 , wherein the descriptor fetch block comprises:
a descriptor queue suitable for storing a descriptor ID corresponding to the descriptor; and
a descriptor fetch part suitable for generating a descriptor address based on the descriptor ID, and providing the descriptor address to the DMA block.

5. The data storage device according to claim 4 , wherein the DMA block reads the descriptor from the working memory based on the descriptor address, and provides the descriptor to the instruction fetch block.

6. The data storage device according to claim 4 , wherein the control unit generates the descriptor and the descriptor ID, and
wherein the descriptor fetch part fetches the descriptor ID in order of generation of the descriptor ID.

7. The data storage device according to claim 3 , wherein the instruction fetch block comprises an instruction fetch part suitable for fetching the instruction set from the instruction memory, and extracting the descriptor parameter corresponding to the instruction set from the descriptor.

8. The data storage device according to claim 7 , wherein the plurality of instruction sets are loaded in the instruction memory during a boot-up operation of the data storage device, and
wherein the instruction fetch part fetches the instruction set based on the address of the instruction set, which is included in the descriptor.

9. The data storage device according to claim 3 , wherein the instruction push block provides a data buffer memory address, which is included in the descriptor, to the DMA block, and
wherein the DMA block provides the data corresponding to the data buffer memory address from the working memory to the signal generation block, or stores data, which is read from the nonvolatile memory device, in the working memory according to the data buffer memory address.

10. The data storage device according to claim 3 , wherein the instruction push block provides the descriptor address included in the descriptor and a state information of the nonvolatile memory device to the DMA block, and
wherein the DMA block stores the state information of the nonvolatile memory device in the control memory according to the descriptor address.

11. The data storage device according to claim 2 , wherein, the instruction set includes one or more instructions arranged in order of a control procedure of the nonvolatile memory device.

12. The data storage device according to claim 1 , wherein the descriptor includes: information about the descriptor;
information about the data stored in the working memory and the control signals used for the memory control unit; and
information about a command, an address, and data used for the nonvolatile memory device.

13. A memory control unit comprising:
a descriptor fetch block suitable for reading a descriptor, wherein the descriptor describes a work for controlling a nonvolatile memory device and includes an address of an instruction set stored in an instruction memory from a working memory;
an instruction fetch block suitable for fetching the instruction set from the instruction memory based on the address of the instruction set included in the descriptor, and adding a descriptor parameter extracted from the descriptor to the fetched instruction set; and
an instruction push block suitable for providing the fetched instruction set and the descriptor parameter that is added to the fetched instruction set to a signal generation block in order to generate control signals for the nonvolatile memory device based on the instruction set and the descriptor parameter,
wherein the instruction set is a set of control signals that are listed in an order of a control procedure of the nonvolatile memory device in order to control the nonvolatile memory device.

14. The memory control unit according to claim 13 , further comprising:
a direct memory access (DMA) block suitable for reading the descriptor and data from the working memory.

15. The memory control unit according to claim 14 , wherein the descriptor fetch block comprises:
a descriptor queue suitable for storing an ID of the descriptor; and
a descriptor fetch part suitable for generating a descriptor address based on the descriptor ID for the DMA block to read the descriptor based on the descriptor address.

16. The memory control unit according to claim 15 , wherein the instruction fetch block comprises an instruction fetch part suitable for fetching the instruction set from the instruction memory based on the address of the instruction set, which is included in the descriptor.

17. The memory control unit according to claim 14 , wherein the instruction push block provides a data buffer memory address, which is included in the descriptor, to the DMA block, and
wherein the DMA block provides the data corresponding to the data buffer memory address from the working memory to the signal generation block, or stores data, which is read from the nonvolatile memory device, in the working memory according to the data buffer memory address, and
wherein the instruction push block provides the descriptor address included in the descriptor and a state information of the nonvolatile memory device to the DMA bl

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Woo
• Kim Kwang Hyun

Classifications

• G06F13/1673 Primary

  using buffers · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F2212/2532

  comprising a plurality of modules · CPC title