Semiconductor package having stacked chips and a heat dissipation part and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9875992-B2
Application number	US-201514821767-A
Country	US
Kind code	B2
Filing date	Aug 9, 2015
Priority date	Sep 11, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate;
a first semiconductor chip mounted on the substrate;
a second semiconductor chip mounted on a top surface of the first semiconductor chip;
a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip;
a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first semiconductor chip and the second semiconductor chip and spaced apart from a bottom surface of the second semiconductor chip; and
an insulating pattern provided between the first semiconductor chip and the second semiconductor chip and covering a sidewall of the connecting bump;
wherein:
the insulating pattern is disposed between an uppermost surface of the first heat dissipation part and the bottom surface of the second semiconductor chip;
the insulating pattern covers a sidewall of the first heat dissipation part;
a thickness of the insulating pattern on the uppermost surface of the first heat dissipation part is smaller than a distance between the top surface of the first semiconductor chip and the bottom surface of the second semiconductor chip;
the first heat dissipation part includes a thermal pad;
the first heat dissipation part further comprises a thermal bump disposed on the thermal pad;
the thermal bump is spaced apart from all conductive structures on the bottom surface of the second semiconductor chip; and
a height of the thermal bump is lower than a height of the connecting bump.

2. The semiconductor package of claim 1 , further comprising:
a connecting pad disposed on the top surface of the first semiconductor chip,
wherein the connecting pad is in contact with the connecting bump.

3. The semiconductor package of claim 2 ,
wherein the thermal pad includes the same material as the connecting pad.

4. The semiconductor package of claim 2 ,
wherein a thickness of the thermal pad is equal to a thickness of the connecting pad.

5. The semiconductor package of claim 1 , further comprising:
an alignment key disposed on the top surface of the first semiconductor chip,
wherein:
the alignment key includes the same material as the thermal pad, and
a thickness of the alignment key is equal to a thickness of the thermal pad.

6. The semiconductor package of claim 1 , wherein:
the first semiconductor chip comprises a through-via, and
the connecting bump is electrically connected to the through-via.

7. The semiconductor package of claim 1 , wherein:
the first semiconductor chip comprises a first heat source adjacent to a bottom surface of the first semiconductor chip, and
the first heat dissipation part overlaps with the first heat source when viewed from a plan view.

8. The semiconductor package of claim 7 , wherein:
the first semiconductor chip comprises a second heat source adjacent to the bottom surface of the first semiconductor chip, and
the first heat dissipation part overlaps with the first heat source and the second heat source when viewed from a plan view.

9. The semiconductor package of claim 1 , further comprising:
a third semiconductor chip mounted on a top surface of the second semiconductor chip; and
a second heat dissipation part disposed on the top surface of the second semiconductor chip and spaced apart from a bottom surface of the third semiconductor chip.

10. The semiconductor package of claim 9 , further comprising:
an upper bump disposed between the second and third semiconductor chips to electrically connect the third semiconductor chip to the second semiconductor chip,
wherein a height of the second heat dissipation part is lower than that of the upper bump.

11. The semiconductor package of claim 9 , wherein:
the first semiconductor chip comprises a first through-via, wherein the connecting bump is electrically connected to the first through-via;
the second semiconductor chip comprises a second through-via, the connecting bump is electrically connected to the second through-via; and
the third semiconductor chip comprises a non through-via semiconductor chip.

12. The semiconductor package of claim 1 , wherein:
the second semiconductor chip comprises integrated circuits adjacent to the bottom surface of the second semiconductor chip, and
at least one of the integrated circuits overlaps with the first heat dissipation part when viewed from a plan view.

13. A semiconductor package comprising:
a substrate;
a first semiconductor chip disposed on the substrate, wherein the first semiconductor chip comprises a through-via;
a second semiconductor chip disposed on the first semiconductor chip;
a connecting bump disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the second semiconductor chip to the first semiconductor chip, wherein the connecting bump is electrically connected to the through-via;
a first pad disposed between the first semiconductor chip and the connecting bump; and
a heat dissipation part disposed on a top surface of the first semiconductor chip between the first semiconductor chip and the second semiconductor chip and spaced apart from a bottom surface of the second semiconductor chip,
wherein the heat dissipation part includes a second pad disposed on the first semiconductor chip and a thermal bump disposed on the second pad; and
an insulating pattern provided between the first semiconductor chip and the second semiconductor chip and covering sidewalls of the connecting bump;
wherein:
the insulating pattern is disposed between an uppermost surface of the heat dissipation part and the bottom surface of the second semiconductor chip;
the uppermost surface of the heat dissipation part is disposed at a higher level than the top surface of the first semiconductor chip;
the thermal bump is spaced apart from all conductive structures on the bottom surface of the second semiconductor chip; and
a height of the thermal bump is lower than a height of the connecting bump.

14. The semiconductor package of claim 13 , wherein:
the second pad includes the same material as the first pad, and
wherein a thickness of the second pad is equal to that of the first pad.

15. A semiconductor package comprising:
a substrate;
a first semiconductor chip disposed on the substrate;
a second semiconductor chip disposed on the first semiconductor chip;
a third semiconductor chip mounted on a top surface of the second semiconductor chip;
a connecting bump disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the second semiconductor chip to the first semiconductor chip;
a first pad disposed between the first semiconductor chip and the connecting bump; and
a thermal dissipation part disposed on a top surface of the first semiconductor chip between the first semiconductor chip and the second semiconductor chip and spaced apart from a bottom surface of the second semiconductor chip,
wherein the thermal dissipation part includes a thermal pad disposed on the first semiconductor chip and a thermal bump disposed on the thermal pad;
an insulating pattern provided between the first semiconductor chip and the second semiconductor chip and covering a sidewall of the connecting bump;
wherein:
the thermal bump is spaced apart from all conductive structures on the bottom surface of the second semiconductor chip;
the insulating pattern is disposed between an uppermost surface of the thermal bump and the bottom surface of the second semiconductor chip;

Assignees

• Heo Junyeong
• Jo Chajea
• Cho Taeje
• Samsung Electronics Co Ltd

Inventors

• Heo Junyeong
• Jo Chajea
• Cho Taeje

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title