Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-9875970-B2
Application number	US-201715413713-A
Country	US
Kind code	B2
Filing date	Jan 24, 2017
Priority date	Apr 25, 2016
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip;
a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip;
vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip,
wherein the first connection member includes a first insulating layer, a first redistribution layer in contact with the second connection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
the first and second redistribution layers are electrically connected to the connection pads.

2. The fan-out semiconductor package of claim 1 , wherein the pattern layer and the vias are integrated with each other without a boundary therebetween.

3. The fan-out semiconductor package of claim 1 , further comprising a metal layer disposed on the inactive surface of the semiconductor chip,
wherein the vias contact the metal layer.

4. The fan-out semiconductor package of claim 1 , further comprising:
a passivation layer covering at least portions of the pattern layer; and
a heat dissipation member attached to the passivation layer.

5. The fan-out semiconductor package of claim 1 , wherein the pattern layer includes patterns electrically insulated from the connection pads of the semiconductor chip.

6. The fan-out semiconductor package of claim 1 , wherein the pattern layer includes a ground pattern.

7. The fan-out semiconductor package of claim 6 , wherein the pattern layer further includes a signal pattern.

8. The fan-out semiconductor package of claim 7 , wherein the first connection member includes a ground pattern, and
the ground pattern of the pattern layer is electrically connected to the ground pattern of the first connection member through the vias.

9. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a redistribution layer of which at least portions are exposed by openings penetrating through the encapsulant, and
the redistribution layer of the first connection member is electrically connected to the connection pads.

10. The fan-out semiconductor package of claim 1 , further comprising a metal layer disposed on a wall of the through-hole.

11. The fan-out semiconductor package of claim 10 , wherein the metal layer extends to an upper portion and a lower portion of the first connection member.

12. The fan-out semiconductor package of claim 1 , wherein the first connection member includes first and second through-holes as the through-hole,
the semiconductor chip is disposed in the first through-hole,
a passive component is disposed in the second through-hole, and
the vias are selectively connected to the inactive surface of the semiconductor chip.

13. The fan-out semiconductor package of claim 1 , wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the third redistribution layer is electrically connected to the connection pads.

14. The fan-out semiconductor package of claim 1 , wherein a lower surface of the first redistribution layer and a lower surface of the first insulating layer have a step therebetween.

15. A fan-out semiconductor package comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip;
a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip;
vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip,
wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the first to third redistribution layers are electrically connected to the connection pads.

16. The fan-out semiconductor package of claim 15 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the fourth redistribution layer is electrically connected to the connection pads.

17. The fan-out semiconductor package of claim 15 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

18. The fan-out semiconductor package of claim 1 , wherein the pattern layer and the vias have thermal conductivity greater than that of the encapsulant.

Assignees

• Samsung Electro Mech

Inventors

• Yi Moon Hee
• Jung Joo Hwan
• Chung Yul Kyo

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/40

  characterised by their materials · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title