Method for making a circuit board

US9872393B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9872393-B2
Application numberUS-201514886581-A
CountryUS
Kind codeB2
Filing dateOct 19, 2015
Priority dateJun 10, 2015
Publication dateJan 16, 2018
Grant dateJan 16, 2018

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A circuit board includes a core layer, at least one passive component, a first and a second conductive wire layers, at least one contact pad, and a resin packing layer. The core layer defines at least one through hole to receive the passive component. The first and the second conductive wire layers are connected to two opposite surfaces of the core layer. Each contact pad is positioned between and connected to one passive component and the first conductive wire layer. The resin packing layer is filled among the core layer, each passive component, each contact pad, the first and the second conductive wire layers. The resin packing layer can connect the first and the second conductive wire layers to the core layer, and connect the core layer, each passive component, and each contact pads to each other.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for making a circuit board comprising: providing a supporting plate comprising a supporting portion and at least one first copper layer connected to at least one surface of the supporting portion; connecting at least one contact pad to a surface of each of the at least one first copper layer away from the supporting portion; connecting at least one passive component to a surface of each of the at least one contact pad away from the first copper layer; forming a first resin layer on a portion of each of the at least one first copper layer besides the passive component; disposing a core layer defining at least one through hole on a surface of each first resin layer away from the first copper layer to allow the passive component to be received in the through hole, and disposing a second resin layer and a second copper layer successively on each core layer and the passive component; pressing the two second copper layer causing the supporting portion, the first copper layer, the contact pad, the passive component, the first resin layer, the core layer, the second resin layer, and the second copper layer to be connected to each other to form a first intermediate product, wherein the first resin layer and the second resin layer flows to fill gaps between the first copper layer, the contact pad, the passive component, the core layer, and the second copper layer, thereby connecting to each other to from a resin packing layer; removing the supporting portion of the first intermediate product to form at least one second intermediate product; defining a plurality of plating holes at a portion of the first copper layer and the second copper layer, and a corresponding portion of the resin packing layer comprised in each of the at least one second intermediate product, an end of each of the plurality of plating holes being closed by one surface of the core layer; and forming a conductive portion in each of the plurality of plating holes which is electrically connected to the first copper layer, the second copper layer, and the core layer; and etching the first copper layer and the second copper layer to form a first conductive wire layer and a second conductive wire layer. 2. The method of claim 1 , wherein after the step of “etching the first copper layer and the second copper layer to form a first conductive wire layer and a second conductive wire layer” further comprises: connecting a solder mask layer to a surface of each of the first conductive wire layer and the second conductive wire layer away from the core layer; and defining a plurality of openings at each solder mask layer. 3. The method of claim 1 , wherein the step of “connecting at least one contact pad to a surface of each of the at least one first copper layer away from the supporting portion” further comprises: forming an electro-plating layer on the surface of the first copper layer by electro-plating; and forming a conductive paste layer on a surface of the electro-plating layer away from the first copper layer by coating a conductive paste, thereby forming the contact pad comprising the electro-plating layer and the conductive paste layer. 4. The method of claim 1 , wherein the first resin layer is made of an adhesive resin composition; the adhesive resin composition comprises adhesive resin selected from a group consisting of polypropylene, polyurethane, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, and polyimide, or any combination thereof. 5. The method of claim 1 , wherein the second resin layer is made of an adhesive resin composition; the adhesive resin composition comprises adhesive resin selected from a group consisting of polypropylene, polyurethane, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, and polyimide, or any combination thereof.

Assignees

Inventors

Classifications

  • by direct electroplating · CPC title

  • by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

  • Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • having cavities, e.g. for mounting components (H05K3/4691 takes precedence) · CPC title

  • H05K1/0298Primary

    Multilayer circuits · CPC title

Patent family

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External sources

Frequently asked questions

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What does patent US9872393B2 cover?
A circuit board includes a core layer, at least one passive component, a first and a second conductive wire layers, at least one contact pad, and a resin packing layer. The core layer defines at least one through hole to receive the passive component. The first and the second conductive wire layers are connected to two opposite surfaces of the core layer. Each contact pad is positioned between …
Who is the assignee on this patent?
Avary Holding (Shenzhen) Co Ltd, Hongqisheng Prec Electronics (Qinhuangdao) Co Ltd, Garuda Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K1/0298. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 16 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).