Solid-state imaging apparatus

Patent metadata

Field	Value
Publication number	US-9871983-B2
Application number	US-201615377613-A
Country	US
Kind code	B2
Filing date	Dec 13, 2016
Priority date	Dec 5, 2012
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A solid-state imaging apparatus includes a pixel including: a photoelectric converter that generates a signal charge corresponding to incident light; a charge storage section that is connected to the photoelectric converter and accumulates signal charge; a reset transistor; an amplifying transistor; and a cutoff transistor, wherein the amplifying transistor and the cutoff transistor form a negative feedback amplifying circuit.

First claim

The invention claimed is:

1. An imaging device comprising,
a pixel including:
a photoelectric converter that generates signal charge corresponding to incident light;
a charge storage section that is electrically connected to the photoelectric converter and accumulates signal charge;
a reset transistor in which one of a source and a drain is electrically connected to the charge storage section; and
an amplifying transistor having a gate which is electrically connected to the charge storage section, wherein:

in a first period when a voltage of the charge storage section is read out,
one of a source and a drain of the amplifier transistor is electrically connected to a first power supply voltage,
the other of the source and the drain of the amplifier transistor is electrically connected to a signal output section that outputs a signal transferred from the pixel, and
a first voltage that causes the reset transistor to be nonconductive state is applied to a gate of the reset transistor, and

in a second period when a voltage of the charge storage section is reset,
the one of the source and the drain of the amplifier transistor is electrically connected to a reference voltage,
the other of the source and the drain of the amplifier transistor is electrically connected to a second power supply voltage via a load, and
a second voltage between the first voltage and a third voltage is applied to the gate of the reset transistor, the third voltage being a voltage that causes the reset transistor to be conductive state.

2. The imaging device according to claim 1 , further comprising:
a first switch that electrically connects the other of the source and the drain of the amplifier transistor to one of the signal output section and the second power supply voltage selectively, wherein:
the load is electrically connected between the amplifier transistor and the first switch.

3. The imaging device according to claim 1 , further comprising:
a second switch that electrically connects the one of the source and the drain of the amplifier transistor to one of the first power supply voltage and the reference voltage selectively.

4. The imaging device according to claim 1 , wherein:
the pixel includes a cutoff transistor in which one of a source and a drain which is electrically connected to the other of the source and the drain of the amplifier transistor, and
the cutoff transistor functions as the load.

5. The imaging device according to claim 4 , wherein the pixel includes a selection transistor electrically connected between the amplifier transistor and the cutoff transistor, one of a source and a drain of the selection transistor being electrically connected to the other of the source and the drain of the amplifier transistor, the other of the source and the drain of the selection transistor being electrically connected to the one of the source and the drain of the cutoff transistor.

6. The imaging device according to claim 4 , wherein the other of the source and the drain of the reset transistor is electrically connected to the one of the source and the drain of the cutoff transistor and the other of the source and the drain of the amplifier transistor.

7. The imaging device according to claim 5 , wherein the other of the source and the drain of the reset transistor is electrically connected to the one of the source and the drain of the cutoff transistor and the other of the source and the drain of the selection transistor.

8. The imaging device according to claim 1 , wherein a voltage value of the reference voltage is zero.

9. The imaging device according to claim 1 , further comprising a controller, wherein
in the first period, the controller causes the one of the source and the drain of the amplifier transistor to be electrically connected to the first power supply voltage, causes the other of the source and the drain of the amplifier transistor to be electrically connected to the signal output section, and causes the first voltage to be applied to the gate of the reset transistor for causing the reset transistor to become nonconductive state, and
in the second period, the controller causes the one of the source and the drain of the amplifier transistor to be electrically connected to the reference voltage, causes the other of the source and the drain of the amplifier transistor to be electrically connected to the second power supply voltage via the load, and causes the second voltage to be applied to the gate of the reset transistor.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Yazawa Keisuke
• Ishii Motonori
• Hirose Yutaka
• Kato Yoshihisa
• Matsunaga Yoshiyuki

Classifications

• H04N25/766

  comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/65 Primary

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title