Solid-state imaging apparatus

Patent metadata

Field	Value
Publication number	US-9554067-B2
Application number	US-201514723498-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Dec 5, 2012
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

The present invention provides a solid-state imaging apparatus that can significantly reduce kTC noise by using a negative feedback amplifying circuit. A solid-state imaging apparatus includes a pixel unit including a plurality of pixels arranged on a semiconductor substrate in a matrix, the pixel unit including, for each column, a source line and a column signal line, each of the plurality of pixels including: a photoelectric conversion unit that generates a signal charge corresponding to incident light; a storage unit storing the signal charge; a reset transistor; an amplifying transistor; and a cutoff transistor, wherein the amplifying transistor and the cutoff transistor form a negative feedback amplifying circuit. With this configuration, kTC noise can significantly be reduced.

First claim

The invention claimed is:

1. A solid-state imaging apparatus comprising:
a pixel unit including a plurality of pixels arranged on a semiconductor substrate in a matrix,
the pixel unit including for each column:
a source line connected to one of a first power supply voltage and a reference potential; and
a column signal line connected to one of a second power supply voltage and a signal output unit outputting a signal from the pixels,

each of the plurality of pixels including:
a photoelectric conversion unit that generates a signal charge corresponding to incident light;
a charge storage unit connected to the photoelectric conversion unit;
a reset transistor having a source and a drain, one of which is connected to the charge storage unit;
an amplifying transistor having a gate that is connected to the charge storage unit, and having a source and a drain, one of which is connected to the source line; and
a cutoff transistor having a source and a drain, one of which is connected to the other one of the source and the drain of the reset transistor and to the other one of the source and the drain of the amplifying transistor, and the other one of which is connected to the column signal line,

wherein
during a first period for discharging a charge in the charge storage unit,
a potential between a third gate potential that allows the cutoff transistor to be conductive and a fourth gate potential that allows the cutoff transistor to be nonconductive is applied to a gate of the cutoff transistor,
a first gate potential that allows the reset transistor to be conductive is applied to a gate of the reset transistor,
the source line is connected to the reference potential, and
the column signal line is connected to the second power supply voltage, and
during a second period in which a negative feedback is performed to the charge storage unit after the first period,
a potential between the first gate potential and a second gate potential that allows the reset transistor to be nonconductive is applied to the gate of the reset transistor, and
the fourth gate potential is applied to the gate of the cutoff transistor.

2. The solid-state imaging apparatus according to claim 1 , wherein
during a third period for generating a signal charge in the photoelectric conversion unit after the second period,
the second gate potential is applied to the gate of the reset transistor,
during a fourth period for reading a pixel signal corresponding to the signal charge of the pixel arranged in an mth (m is a natural number) row to the column signal line after the third period,
the third gate potential is applied to the gate of the cutoff transistor of the pixel arranged in the mth row,
during a fifth period for resetting the potential of the charge storage unit of the pixel arranged in the mth row after the fourth period,
a drive similar to that during the first period and a drive similar to that during the second period are performed to the pixel arranged in the mth row, and
during a sixth period for reading a reset signal of the pixel arranged in the mth row to the column signal line after the fifth period,
the second gate potential is applied to the gate of the reset transistor of the pixel arranged in the mth row, and
the third gate potential is applied to the gate of the cutoff transistor of the pixel arranged in the mth row.

3. The solid-state imaging apparatus according to claim 2 , wherein
the source line is connected to the first power supply voltage during the fourth period and the sixth period.

4. A solid-state imaging apparatus comprising:
a pixel unit including a plurality of pixels arranged on a semiconductor substrate in a matrix,
the pixel unit including for each column:
a source line connected to one of a first power supply voltage and a reference potential; and
a column signal line connected to one of a second power supply voltage and a signal output unit outputting a signal from the pixels,

each of the plurality of pixels including:
a photoelectric conversion unit that generates a signal charge corresponding to incident light;
a charge storage unit connected to the photoelectric conversion unit;
a reset transistor having a source and a drain, one of which is connected to the charge storage unit;
an amplifying transistor having a gate that is connected to the charge storage unit, and having a source and a drain, one of which is connected to the source line;
a cutoff transistor having a source and a drain, one of which is connected to the other one of the source and the drain of the reset transistor and to the other one of the source and the drain of the amplifying transistor, and the other one of which is connected to the column signal line; and
a selection transistor having a source and a drain, one of which is connected to the other one of the source and the drain of the amplifying transistor, and the other one of which is connected to the other one of the source and the drain of the reset transistor and to the one of the source and the drain of the cutoff transistor,

wherein
during a first period for discharging a charge in the charge storage unit,
a potential between a third gate potential that allows the cutoff transistor to be conductive and a fourth gate potential that allows the cutoff transistor to be nonconductive is applied to a gate of the cutoff transistor,
a fifth gate potential that allows the selection transistor to be conductive is applied to a gate of the selection transistor,
a first gate potential that allows the reset transistor to be conductive is applied to a gate of the reset transistor,
the source line is connected to the reference potential, and
the column signal line is connected to the second power supply voltage, and
during a second period in which a negative feedback is performed to the charge storage unit after the first period,
a potential between the first gate potential and a second gate potential that allows the reset transistor to be nonconductive is applied to the gate of the reset transistor,
a potential between the fifth gate potential and a sixth gate potential that allows the selection transistor to be nonconductive is applied to the gate of the selection transistor, and
the fourth gate potential is applied to the gate of the cutoff transistor.

5. The solid-state imaging apparatus according to claim 4 , wherein
during a third period for generating a signal charge in the photoelectric conversion unit after the second period,
the second gate potential is applied to the gate of the reset transistor,
the sixth gate potential is applied to the gate of the selection transistor, and
the source line is connected to the first power supply voltage,
during a fourth period for reading a pixel signal corresponding to the signal charge of the pixel arranged in an mth (m is a natural number) row to the column signal line after the third period,
the third gate potential is applied to the gate of the cutoff transistor of the pixel arranged in the mth row, and
the fifth gate potential is applied to the gate of the selection transistor of the pixel arranged in the mth row,
during a fifth period for resetting the potential of the charge storage unit of the pixel arranged in the mth row after the fourth period,
a drive similar to that during the first period and a drive similar to that during the second period are performed to the pixel arranged in the mth row, and
during a sixth period for reading a reset signal of the pixel arranged in the mth row to the column signal line after the fifth period,
the second gate potential is applied to the gate of the reset transistor of the pixel arranged in the mth row,
the third gate potential is applied to the gate of the cutoff transistor of the pixel arranged in the mth row, an

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Yazawa Keisuke
• Ishii Motonori
• Hirose Yutaka
• Kato Yoshihisa
• Matsunaga Yoshiyuki

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/766

  comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/65 Primary

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title