Solid-state imaging device

Patent metadata

Field	Value
Publication number	US-9344654-B2
Application number	US-201514613122-A
Country	US
Kind code	B2
Filing date	Feb 3, 2015
Priority date	Aug 9, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A solid-state imaging device includes pixels each including: a charge storage portion; an amplifier transistor having a gate connected to the charge storage portion; a selection transistor having a source connected to a source of the amplifier transistor and a drain connected to a column signal line; and a reset transistor having a source connected to the charge storage portion and a drain connected to the column signal line, and further includes a control unit which applies to a gate of the selection transistor a first voltage to place the selection transistor in a conductive state and applies to a gate of the reset transistor a second voltage to place the reset transistor in a non-conductive state in a pixel signal readout period, and applies to the gate of the selection transistor a voltage intermediate between the first voltage and the second voltage in a charge storage portion resetting period.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
a semiconductor substrate;
a pixel portion which includes pixels in rows and columns above the semiconductor substrate; and
a plurality of column signal lines provided for each of the columns of the pixel portion,
the pixels each including:
a photoelectric converting film;
a pixel electrode disposed along a surface of the photoelectric converting film, the surface facing the semiconductor substrate;
a transparent electrode disposed along a surface of the photoelectric converting film opposite the surface along which the pixel electrode is disposed;
a charge storage portion electrically connected to the pixel electrode, the charge storage portion storing signal charge from the photoelectric converting film;
an amplifier transistor which outputs a pixel signal dependent on quantity of the signal charge in the charge storage portion;
a reset transistor which resets electric potential of the charge storage portion; and
a selection transistor which determines a timing at which the amplifier transistor is to output the pixel signal,
the solid-state imaging device further comprising
a control unit configured to apply to a gate terminal of the selection transistor a first voltage which places the selection transistor in a conductive state and apply to a gate terminal of the reset transistor a second voltage which places the reset transistor in a non-conductive state in a first time period where the pixel signal dependent on the quantity of the signal charge in the photoelectric converting film is read out, and apply to the gate terminal of the selection transistor a third voltage which is an intermediate value between the first voltage and the second voltage in a second time period where the charge storage portion is reset.

2. The solid-state imaging device according to claim 1 , wherein
the control unit is configured to apply to the gate terminal of the reset transistor a voltage which continuously changes from the first voltage to the second voltage in the second time period.

3. The solid-state imaging device according to claim 1 , wherein
one of a source and a drain of the amplifier transistor is connected to a power potential feeding line, and
the control unit is configured to feed a power voltage to the power potential feeding line in the first time period and feed a ground voltage to the power potential feeding line in the second time period.

4. The solid-state imaging device according to claim 1 , further comprising:
a load transistor having a source and a drain one of which is connected to a first column signal line included in the plurality of column signal lines via a switch;
an amplifier connected to the one of the source and the drain of the load transistor; and
a capacitor connected to the amplifier, wherein
an output of the amplifier is connected via the capacitor to a gate terminal of the amplifier transistor.

5. The solid-state imaging device according to claim 3 , wherein
one end of the power potential feeding line is connected to a source of the power voltage via a first switch,
the other end of the power potential feeding line is connected to a source of the ground voltage via a second switch,
the first switch is in the conductive state and the second switch is in the non-conductive state in the first time period, and
the first switch is in the non-conductive state and the second switch is in the conductive state in the second time period.

6. The solid-state imaging device according to claim 3 , wherein
one end of the power potential feeding line is selectively connected to a source of the power voltage or a source of the ground voltage,
the one end of the power potential feeding line is connected to the source of the power voltage in the first time period, and
the one end of the power potential feeding line is connected to the source of the ground voltage in the second time period.

7. The solid-state imaging device according to claim 1 , wherein
one of a source and a drain of the reset transistor is connected to a gate terminal of the amplifier transistor, and
the other of the source and the drain of the reset transistor is connected to one of a source and a drain of the amplifier transistor.

8. The solid-state imaging device according to claim 1 , further comprising
a load transistor, wherein
one of a source and a drain of the load transistor is connected to one of a source and a drain of the selection transistor, and
the other of the source and the drain of the load transistor is connected to a first column signal line included in the plurality of column signal lines.

9. The solid-state imaging device according to claim 8 , wherein
the one of the source and the drain of the load transistor is connected to the one of the source and the drain of the selection transistor of an adjacent pixel.

10. The solid-state imaging device according to claim 1 further comprising
an amplifier having an input terminal connected to a first column signal line included in the plurality of column signal lines, wherein
the amplifier has an output terminal connected to a constant voltage source via a switch.

11. The solid-state imaging device according to claim 1 , wherein
the pixels are disposed between the photoelectric converting film and the substrate.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Ishii Motonori

Classifications

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• H04N25/709 Primary

  Circuitry for control of the power supply · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/8063

  Microlenses · CPC title

• H10F39/8053

  Colour filters · CPC title