Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9871056-B2
Application number	US-201615389883-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	Mar 13, 2008
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a region including a plurality of transistors, each of the plurality of transistors in the region forming part of circuitry associated with execution of one or more logic functions, the region including at least nine conductive structures formed within the semiconductor chip, some of the at least nine conductive structures forming at least one transistor gate electrode,
each of the at least nine conductive structures respectively having a corresponding top surface, wherein an entirety of a periphery of the corresponding top surface is defined by a corresponding first end, a corresponding second end, a corresponding first edge, and a corresponding second edge, such that a total distance along the entirety of the periphery of the corresponding top surface is equal to a sum of a total distance along the corresponding first edge and a total distance along the corresponding second edge and a total distance along the corresponding first end and a total distance along the corresponding second end,
wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding first end,
wherein the total distance along the corresponding first edge is greater than two times the total distance along the corresponding second end,
wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding first end,
wherein the total distance along the corresponding second edge is greater than two times the total distance along the corresponding second end,
wherein the corresponding first end extends from the corresponding first edge to the corresponding second edge and is located principally within a space between the corresponding first and second edges,
wherein the corresponding second end extends from the corresponding first edge to the corresponding second edge and is located principally within the space between the corresponding first and second edges,
the top surfaces of the at least nine conductive structures co-planar with each other,
each of the at least nine conductive structures having a corresponding lengthwise centerline oriented in a first direction along its top surface and extending from its first end to its second end,
each of the at least nine conductive structures having a length as measured along its lengthwise centerline from its first end to its second end,
wherein the first edge of each of the at least nine conductive structures is substantially straight,
wherein the second edge of each of the at least nine conductive structures is substantially straight,
each of the at least nine conductive structures having both its first edge and its second edge oriented substantially parallel to its lengthwise centerline,
each of the at least nine conductive structures having a width measured in a second direction perpendicular to the first direction at a midpoint of its lengthwise centerline,
each of the first direction and the second direction oriented substantially parallel to the co-planar top surfaces of the at least nine conductive structures,
wherein the at least nine conductive structures are positioned in a side-by-side manner such that each of the at least nine conductive structures is positioned to have at least a portion of its length beside at least a portion of the length of another of the at least nine conductive structures,
wherein the width of each of the at least nine conductive structures is less than 45 nanometers, each of the at least nine conductive structures positioned such that a distance as measured in the second direction between its lengthwise centerline and the lengthwise centerline of at least one other of the at least nine conductive structures is substantially equal to a first pitch that is less than or equal to about 193 nanometers,
wherein the at least nine conductive structures includes a first conductive structure, the first conductive structure including a portion that forms a gate electrode of a first transistor of a first transistor type, the first conductive structure also including a portion that forms a gate electrode of a first transistor of a second transistor type,
wherein the at least nine conductive structures includes a second conductive structure, the second conductive structure including a portion that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second conductive structure is of the first transistor type,
wherein the at least nine conductive structures includes a third conductive structure, the third conductive structure including a portion that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third conductive structure is of the second transistor type,
wherein the at least nine conductive structures includes a fourth conductive structure, the fourth conductive structure including a portion that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth conductive structure is of the first transistor type,
wherein the at least nine conductive structures includes a fifth conductive structure, the fifth conductive structure including a portion that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth conductive structure is of the second transistor type,
wherein the at least nine conductive structures includes a sixth conductive structure, the sixth conductive structure including a portion that forms a gate electrode of a fourth transistor of the first transistor type, the sixth conductive structure also including a portion that forms a gate electrode of a fourth transistor of the second transistor type,
wherein the first transistor of the first transistor type includes a first diffusion terminal and the second transistor of the first transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the first transistor type electrically connected to the first diffusion terminal of the second transistor of the first transistor type through a first electrical connection,
wherein the first transistor of the second transistor type includes a first diffusion terminal, and the second transistor of the second transistor type includes a first diffusion terminal, the first diffusion terminal of the first transistor of the second transistor type electrically connected to the first diffusion terminal of the second transistor of the second transistor type through a second electrical connection,
wherein the second transistor of the first transistor type includes a second diffusion terminal, and the third transistor of the first transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the first transistor type electrically connected to the first diffusion terminal of the third transistor of the first transistor type through a third electrical connection,
wherein the second transistor of the second transistor type includes a second diffusion terminal, and the third transistor of the second transistor type includes a first diffusion terminal, the second diffusion terminal of the second transistor of the second transistor type electrically connected to the first diffusion terminal of the third transistor of the second transistor type through a fourth electrical connection,
wherein the third transistor of the first transistor type includes a second diffusion terminal, and the fourth transistor of the first transistor type includes a first diffusion terminal, the second diffusion terminal of the third transistor of the first transistor

Assignees

• Tela Innovations Inc

Inventors

• Becker Scott T
• Mali Jim
• Lambert Carole

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title