Memory devices having signal routing structures at bonding interfaces
US-2024404976-A1 · Dec 5, 2024 · US
US9035359B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9035359-B2 |
| Application number | US-201414304778-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 13, 2014 |
| Priority date | Mar 9, 2006 |
| Publication date | May 19, 2015 |
| Grant date | May 19, 2015 |
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A first linear-shaped conductive structure (LCS) forms gate electrodes (GE's) of a first transistor of a first transistor type and a first transistor of a second transistor type. A second LCS forms a GE of a second transistor of the first transistor type. A third LCS forms a GE of a second transistor of the second transistor type. A fourth LCS forms a GE of a third transistor of the first transistor type. A fifth LCS forms a GE of a third transistor of the second transistor type. A sixth LCS forms a GE of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. The second, third, fourth, and fifth LCS's have respective electrical connection areas arranged relative to the inner region.
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What is claimed is: 1. A semiconductor chip, comprising: a region including at least seventeen linear-shaped conductive structures oriented to extend lengthwise in a first direction, each of the at least seventeen linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction, each of the at least seventeen linear-shaped conductive structures positioned such that a distance as measured in a second direction between its lengthwise…
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