Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods

US9035359B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9035359-B2
Application numberUS-201414304778-A
CountryUS
Kind codeB2
Filing dateJun 13, 2014
Priority dateMar 9, 2006
Publication dateMay 19, 2015
Grant dateMay 19, 2015

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Abstract

Official abstract text for this publication.

A first linear-shaped conductive structure (LCS) forms gate electrodes (GE's) of a first transistor of a first transistor type and a first transistor of a second transistor type. A second LCS forms a GE of a second transistor of the first transistor type. A third LCS forms a GE of a second transistor of the second transistor type. A fourth LCS forms a GE of a third transistor of the first transistor type. A fifth LCS forms a GE of a third transistor of the second transistor type. A sixth LCS forms a GE of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. The second, third, fourth, and fifth LCS's have respective electrical connection areas arranged relative to the inner region.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor chip, comprising: a region including at least seventeen linear-shaped conductive structures oriented to extend lengthwise in a first direction, each of the at least seventeen linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction, each of the at least seventeen linear-shaped conductive structures positioned such that a distance as measured in a second direction between its lengthwise…

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What does patent US9035359B2 cover?
A first linear-shaped conductive structure (LCS) forms gate electrodes (GE's) of a first transistor of a first transistor type and a first transistor of a second transistor type. A second LCS forms a GE of a second transistor of the first transistor type. A third LCS forms a GE of a second transistor of the second transistor type. A fourth LCS forms a GE of a third transistor of the first trans…
Who is the assignee on this patent?
Tela Innovations Inc
What technology area does this patent fall under?
Primary CPC classification H10D84/907. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 19 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).