Feeding overlay data of one layer to next layer for manufacturing integrated circuit

Patent metadata

Field	Value
Publication number	US-9871001-B2
Application number	US-201615145789-A
Country	US
Kind code	B2
Filing date	May 3, 2016
Priority date	May 3, 2016
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the target portion for the respective exposure field by an exposure system. The overlay of the first layer lithography pattern and the target portion is measured by the set of overlay marks of each exposure field to obtain first overlay data for the respective exposure field by a measuring system. The first overlay data is fed to form a second layer lithography pattern.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit, comprising:
providing a substrate comprising a plurality of exposure fields, and each of the exposure fields comprising a target portion and a set of overlay marks;
exposing the substrate to form a first layer lithography pattern on the target portion for the respective exposure field by an exposure system;
measuring an overlay of the first layer lithography pattern and the target portion by the set of overlay marks of each exposure field to obtain first overlay data for the respective exposure field by a measuring system; and
feeding the first overlay data to form a second layer lithography pattern with different weightings in different directions by the measuring system, wherein the first layer lithography pattern and the second layer lithography pattern are formed in different layers.

2. The method of manufacturing the integrated circuit according to claim 1 , further comprising:
feeding the first overlay data as an alignment data to form the second layer lithography pattern.

3. The method of manufacturing the integrated circuit according to claim 1 , further comprising:
re-calculating the first overlay data and an alignment data of the second layer lithography pattern to form the second layer lithography pattern.

4. The method of manufacturing the integrated circuit according to claim 3 , wherein the first overlay data and the alignment data of the second layer lithography pattern are utilized with the different weightings.

5. The method of manufacturing previously presented the integrated circuit according to claim 1 , further comprising:
etching the substrate by the first layer lithography pattern after measuring the overlay of the first layer lithography pattern and the target portion.

6. The method of manufacturing the integrated circuit according to claim 1 , further comprising:
depositing at least a film on the substrate after measuring the overlay of the first layer lithography pattern and the target portion.

7. The method of manufacturing the integrated circuit according to claim 1 , further comprising:
measuring an overlay of the second layer lithography pattern and the target portion.

8. The method of manufacturing the integrated circuit according to claim 7 , further comprising:
etching the substrate by the second layer lithography pattern after measuring the overlay of the second layer lithography pattern and the target portion.

9. The method of manufacturing the integrated circuit according to claim 7 , further comprising:
depositing at least a film on the substrate after measuring the overlay of the second layer lithography pattern and the target portion.

10. The method of manufacturing the integrated circuit according to claim 1 , wherein each of the exposure fields comprises at least one alignment mark.

11. The method of manufacturing the integrated circuit according to claim 10 , wherein each of the exposure fields only has one single alignment mark.

12. The method of manufacturing the integrated circuit according to claim 10 , further comprising:
measuring the alignment mark of each exposure field to obtain alignment data for the respective exposure field by the measuring system before exposing the substrate.

13. The method of manufacturing the integrated circuit according to claim 12 , further comprising:
feeding the alignment data to form the second layer lithography pattern.

14. The method of manufacturing the integrated circuit according to claim 13 , wherein the first overlay data and the alignment data are utilized with the different weightings to form the second layer lithography pattern.

15. The method of manufacturing the integrated circuit according to claim 13 , wherein the first overlay data, the alignment data and an alignment data of the second layer lithography pattern are utilized with the different weightings to form the second layer lithography pattern.

16. The method of manufacturing the integrated circuit according to claim 1 , wherein the directions comprise a first direction and a second direction.

17. The method of manufacturing the integrated circuit according to claim 16 , wherein the first direction is orthogonal to the second direction.

Assignees

• United Microelectronics Corp

Inventors

• Liou En-Chiuan

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title