Forming CMOSFET structures with different contact liners

Patent metadata

Field	Value
Publication number	US-9870958-B2
Application number	US-201615295485-A
Country	US
Kind code	B2
Filing date	Oct 17, 2016
Priority date	Aug 19, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second trench contact over a second source/drain region of a second transistor; depositing a first liner material within the first trench contact; and depositing a second liner material within the second trench contact; wherein the first liner material and the second liner material include different materials.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first trench contact arranged on a top surface of a first source/drain region comprising a first metal liner disposed within the first trench contact, the first metal liner disposed directly on sidewalls of the first trench contact;
a second trench contact arranged on a top surface of a second source/drain region comprising a second metal liner disposed within the second trench contact; and
a mask arranged only over the first trench contact, a material of the mask disposed directly on the first metal liner to fill the first trench contact;
wherein the first metal liner and the second metal liner comprise different materials, and the second trench contact is open such that the second metal liner is exposed.

2. The semiconductor device of claim 1 , wherein the first metal liner comprises a bilayer of more than one material.

3. The semiconductor device of claim 1 , wherein the second metal liner comprises a bilayer of more than one material.

4. The semiconductor device of claim 1 wherein the first metal liner and the second metal liner comprise a bilayer of more than one material.

5. The semiconductor device of claim 1 , wherein the first metal liner comprises titanium, titanium nitride, or a combination thereof.

6. The semiconductor device of claim 1 , wherein the second metal liner comprises cobalt, titanium, titanium nitride, cobalt titanium, nickel, platinum, nickel platinum titanium, or any combination thereof.

7. The semiconductor device of claim 1 , wherein the first trench contact is a portion of a NFET.

8. The semiconductor device of claim 7 , wherein the second trench contact is a portion of a PFET.

9. The semiconductor device of claim 1 , wherein the mask is a hard mask.

10. The semiconductor device of claim 1 , wherein the mask is a lithographic stack.

11. The semiconductor device of claim 1 , wherein the first metal liner is a bilayer of titanium and titanium nitride.

12. The semiconductor device of claim 1 , wherein the first metal liner has a contact resistance of less than 1×10 −8 ohm·cm 2 .

13. The semiconductor device of claim 1 , wherein the first source/drain region and the second source/drain region comprise epitaxial material.

14. The semiconductor device of claim 13 , wherein the epitaxial material is epitaxial silicon.

15. The semiconductor device of claim 13 , wherein the epitaxial material is epitaxial silicon germanium.

16. The semiconductor device of claim 1 , wherein the first metal liner directly contacts the first source/drain region.

17. The semiconductor device of claim 1 , wherein the second metal liner directly contacts the second source/drain region.

18. The semiconductor device of claim 1 , wherein the first trench contact and the second trench contact are formed on the same substrate.

Assignees

• IBM
• Int Business Machinces Corporation

Inventors

• Cheng Kangguo
• Liu Zuoguang
• Yamashita Tenko

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title