Forming CMOSFET structures with different contact liners

Patent metadata

Field	Value
Publication number	US-9502309-B1
Application number	US-201514964900-A
Country	US
Kind code	B1
Filing date	Dec 10, 2015
Priority date	Aug 19, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second trench contact over a second source/drain region of a second transistor; depositing a first liner material within the first trench contact; and depositing a second liner material within the second trench contact; wherein the first liner material and the second liner material include different materials.

First claim

What is claimed is:

1. A method of making a semiconductor device, the method comprising:
forming a first trench contact over a first source/drain region of a first transistor;
forming a second trench contact over a second source/drain region of a second transistor;
depositing a first liner material within the first trench contact, the first liner material comprising a bilayer of materials; and
depositing a second liner material within the second trench contact, the second liner material comprising a bilayer of materials;
wherein the first liner material comprising the bilayer of materials and the second liner material comprising the bilayer of materials comprise different materials; and the first liner material is deposited in both the first and second trench contacts, followed by filling the first and second trench contacts with a sacrificial material and disposing a mask over the first trench contact.

2. The method of claim 1 , wherein the first liner material comprises titanium, titanium nitride, or a combination thereof.

3. The method of claim 1 , wherein the second liner material comprises cobalt, titanium, titanium nitride, cobalt titanium, nickel, platinum, nickel platinum titanium, or any combination thereof.

4. The method of claim 1 , further comprising removing the sacrificial material and the first liner material from the second trench contact, removing the mask, and then depositing the second liner material and filling the second trench contact with a contact metal.

5. The method of claim 4 , further comprising removing the sacrificial material from the first trench contact and filling the first trench contact with another contact metal.

6. A method of making a semiconductor device, the method comprising:
forming a first trench contact over a first source/drain region of a first transistor;
forming a second trench contact over a second source/drain region of a second transistor;
depositing a first liner material within the first and second trench contacts;
filling the first and second trench contacts with a sacrificial material;
disposing a first mask over the first trench contact;
removing the sacrificial material and the first liner material from the second trench contact that is not covered by the first mask;
removing the first mask and depositing a second liner material within the second trench contact and over the first trench contact;
disposing a second mask over the second trench contact and removing the second liner material and the sacrificial material from the first trench contact; and
removing the second mask and filling the first and second trench contacts with a contact metal;
wherein the first liner material and the second liner material comprise different materials.

7. The method of claim 6 , wherein the sacrificial material is amorphous carbon.

8. The method of claim 6 , wherein the first liner material, the second liner material, or both the first liner material and the second liner material comprise a bilayer of different materials.

9. The method of claim 6 , wherein the first liner material comprises titanium, titanium nitride, or a combination thereof.

10. The method of claim 6 , wherein the second liner material comprises cobalt, titanium, titanium nitride, cobalt titanium, nickel, platinum, nickel platinum titanium, or any combination thereof.

11. The method of claim 6 , wherein the first transistor is an NFET.

12. The method of claim 6 , wherein the second transistor is a PFET.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Liu Zuoguang
• Yamashita Tenko

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title