Methods of forming nanosheets on lattice mismatched substrates

Patent metadata

Field	Value
Publication number	US-9870940-B2
Application number	US-201615066177-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Aug 3, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.

First claim

What is claimed is:

1. A method of forming nanosheets for a semiconductor device, the method comprising:
providing a silicon on insulator (SOI) handle wafer, the SOI handle wafer including a silicon layer and a dielectric layer on the silicon layer;
providing a first donor wafer;
bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure;
debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and
bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.

2. The method of claim 1 , further comprising:
providing a mask on a surface of the final wafer; and
etching the final wafer according to the mask to provide vertical trenches therein.

3. The method of claim 2 , wherein etching is followed by removing the plurality of dielectric layers from between the plurality of silicon or non-silicon nanosheets.

4. The method of claim 1 , wherein the dielectric layers comprise oxide layers and wherein removing comprises removing the oxide layers using a hydrofluoric (HF) solution.

5. The method of claim 1 , wherein the dielectric layers comprises one of SiO 2 , Al 2 O 3 and GeO 2 layers.

6. The method of claim 1 , wherein the silicon or non-silicon nanosheets comprise one of strained or unstrained silicon, strained or unstrained germanium, strained or unstrained silicon-germanium, Group III elements, Group IV elements, Group V elements and combinations thereof.

7. The method of claim 1 , wherein a thickness of the handle wafer including the silicon or non-silicon nanosheets and the dielectric layer is selected based on a desired thickness and spacing of a resulting nanosheet.

8. The method of claim 7 :
wherein the thickness of the silicon or non-silicon nano sheet is from about 3 nm to about 20 nm; and
wherein the thickness of the dielectric layer is from about 5 nm to about 20 nm.

9. The method of claim 1 :
wherein the donor wafer has a thermally oxidized top layer; and
wherein a thickness of the thermally oxidized top layer is from about 5 nm to about 20 nm.

10. The method of claim 1 , further comprising implanting hydrogen ions into a surface of the donor wafer to a depth of from about 10 nm to about 50 nm.

11. The method of claim 1 , wherein bonding the SOI handle wafer and the first donor wafer is preceded by cleaning surfaces of the SOI handle wafer and the first donor wafer to remove surface contaminants thereon.

12. The method of claim 1 , wherein the plurality of nanosheets are substantially defect-free.

13. The method of claim 1 , further comprising tuning a crystal orientation of each layer of the plurality of nanosheets.

14. The method of claim 1 , further comprising one of tuning a strained layer of the plurality of nanosheets.

15. The method of claim 1 , wherein a thickness of the device has no restrictions based on a critical thickness hc.

16. A method of forming nanosheets for a semiconductor device, the method comprising:
providing a silicon on insulator (SOI) handle wafer, the SOI handle wafer including a silicon layer and an SiO 2 layer on the silicon layer;
providing a first silicon donor wafer;
bonding the SOI handle wafer and the first silicon donor wafer together to provide a bonded structure;
debonding the bonded structure to provide an intermediate wafer including a plurality of silicon nanosheets and a plurality of SiO 2 layers alternately stacked; and
bonding the intermediate wafer to a second silicon donor wafer to provide a final wafer including a plurality of silicon nanosheets and a plurality of SiO 2 layers alternately stacked, wherein the final wafer includes at least one more pair of silicon and SiO 2 layers than the intermediate wafer.

17. The method of claim 16 , wherein the plurality of silicon nanosheets are substantially defect-free.

18. The method of claim 16 , further comprising:
providing a mask on a surface of the final wafer;
etching the final wafer according to the mask to provide vertical trenches therein; and
removing the plurality of SiO 2 layers from between the plurality of silicon nanosheets.

19. A method of forming nanosheets for a semiconductor device, the method comprising:
providing a silicon on insulator (SOI) handle wafer, the SOI handle wafer including a non-silicon layer and a dielectric layer on the silicon layer;
providing a first non-silicon donor wafer;
bonding the SOI handle wafer and the first non-silicon donor wafer together to provide a bonded structure;
debonding the bonded structure to provide an intermediate wafer including a plurality of non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and
bonding the intermediate wafer to a second non-silicon donor wafer to provide a final wafer including a plurality of non-silicon nanosheets and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of non-silicon and dielectric layers than the intermediate wafer.

20. The method of claim 19 , wherein the plurality of nanosheets are substantially defect-free.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark
• Obradovic Borna

Classifications

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/282

  of inorganic materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title