Test pad structure, a pad structure for inspecting a semiconductor chip and a wiring substrate for a tape packaging having the same

Patent metadata

Field	Value
Publication number	US-9869717-B2
Application number	US-201615218515-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Jun 25, 2008
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A test pad structure includes a plurality of test pads and a plurality of connection leads. The test pads are sequentially arranged from a wiring pattern on a substrate and in rows parallel with one another. The test pads include first and second groups of test pads, the first group having at least one pad and the second group having at least two pads. The connection leads extend from end portions of the wiring pattern to be connected to the test pads. The connection leads include at least one inner lead passing between the at least two pads of the second group and arranged in a first row closest to the first group. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group arranged in a second row next to the first row.

First claim

What is claimed is:

1. A method of manufacturing a chip-on-film (COF) device, the method comprising:
providing a base film including a package region, a test pad region and a cutting region, the cutting region being disposed between the package region and the test pad region, the package region including a wiring pattern formed with metal thin film, the test pad region including a plurality of test pads, and the plurality of test pads being connected to the wiring pattern with a plurality of connection leads;
mounting a semiconductor device on the package region, thereby connecting a pad of the semiconductor device with the wiring pattern;
inspecting the semiconductor device using the plurality of test pads; and
cutting out the test pad region from the base film along the cutting region,
wherein the plurality of test pads are sequentially arranged from the wiring pattern on the base film and arranged in rows parallel with one another, the plurality of test pads including a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two first pads and at least two second pads, the at least two first pads arranged in a second row parallel with the first row, and the at least two second pads arranged in a third row parallel with the first row, and the plurality of connection leads extends from end portions of the wiring pattern to be connected to the plurality of test pads, the plurality of the connection leads including a first group of connection leads connected to the first group of the test pads and a second group of connection leads having first leads and second leads, the first leads connected to the at least two first pads, and one second lead of the second leads passing between the at least two first pads to be connected to at least one of the at least two second pads arranged in the third row next to the second row.

2. The method of claim 1 , wherein the at least two first pads of the second group arranged in the second row have a first plane area, and the at least two second pads of the second group in the third row have a second plane area greater than the first plane area.

3. The method of claim 1 , wherein the second group of the test pads are arranged to be symmetric with respect to a middle line that extends in a direction where the first group of the test pads are arranged.

4. The method of claim 1 , wherein the one second lead includes a folded portion inclined from a direction where the first group of the test pads are arranged, the folded portion passing between the first group of the test pads and the pad of the second group of the test pads arranged in the second row.

5. The method of claim 1 , wherein the at least two pads of the second group arranged in the second row are spaced apart from each other by a space required for the one second lead.

6. The method of claim 1 , wherein the plurality of test pads are arranged in six rows.

7. The method of claim 1 , wherein the semiconductor device comprises a driving circuit for driving a display device.

8. The method of claim 1 , wherein the metal thin film is comprised at least one of copper (Cu), gold (Au), tin (Sn), lead (Pb), silver (Ag), and nickel (Ni).

9. The method of claim 1 , wherein one end of the wiring pattern is connected to the plurality of connection leads and another end of the wiring pattern is connected to the pad of the semiconductor device.

10. The method of claim 1 , wherein outer edges of the at least one pad arranged in the first row and the at least two first pads arranged in the second row are contained within outer edges of the at least two second pads arranged in the third row.

11. A method of manufacturing a display device, the method comprising:
providing a base film including a package region, a first test pad region, a second test pad region, a first cutting region and a second cutting region, the first cutting region being disposed between the package region and the first test pad region, the second cutting region being disposed between the package region and the second test pad region, the package region including a first wiring pattern and a second wiring pattern formed with metal thin film, the first test pad region including a plurality of input test pads, and the plurality of input test pads being connected to the first wiring pattern with a plurality of first connection leads, the second test pad region including a plurality of output test pads, and the plurality of output test pads being connected to the second wiring pattern with a plurality of second connection leads;
mounting a semiconductor device on the package region, thereby connecting a pad of the semiconductor device with the first wiring pattern and the second wiring pattern;
inspecting the semiconductor device using the first test pad region and the second test pad region;
separating out the first test pad region and the second test pad region by cutting the first cutting region and the second cutting region, respectively;
connecting the first connection leads to a controller device to control the semiconductor device; and
connecting the second connection leads to a display panel,
wherein the plurality of output test pads are sequentially arranged from the second wiring pattern on the base film and arranged in rows parallel with one another, the plurality of output test pads including a first group of test pads having at least one pad arranged in a first row, and a second group of test pads having at least two first pads and at least two second pads, the at least two first pads arranged in a second row parallel with the first row, and the at least two second pads arranged in a third row parallel with the first row, and the plurality of second connection leads extends from end portions of the second wiring pattern to be connected to the plurality of output test pads, the plurality of second connection leads including a first group of connection leads connected to the first group of the test pads and a second group of connection leads having first leads and second leads, the first leads connected to the at least two first pads, and one second lead of the second leads passing between the at least two first pads to be connected to at least one of the at least two second pads arranged in the third row next to the second row.

12. The method of claim 11 , wherein the plurality of input test pads are sequentially arranged from the first wiring pattern on the base film and arranged in rows parallel with one another, the plurality of input test pads including a first group of test pads having at least one pad arranged in a first row, and a second group of test pads having at least two first pads and at least two second pads, the at least two first pads arranged in a second row parallel with the first row, the at least two second pads arranged in a third row parallel with the first row, and the plurality of first connection leads extends from end portions of the first wiring pattern to be connected to the plurality of input test pads, the plurality of first connection leads including a first group of connection leads connected to the first group of the test pads and a second group of connection leads having first leads and second leads, the first leads connected to the at least two first pads, and one of the second leads passing between the at least two first pads to be connected to at least one of the at least two second pads arranged in the third row next to the second row.

13. The method of claim 11 , wherein the second group of the test pads are arranged to be symmetric with respect to a middle line that extends in a direction where the first grou

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Lim So-Young
• Lee Sang-Heui

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W70/688

  Flexible insulating substrates · CPC title

• H10P74/00 Primary

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• H01L22/32

  Electricity · mapped topic

• H01L23/4985

  Electricity · mapped topic