System and method for a vertical tunneling field-effect transistor cell

Patent metadata

Field	Value
Publication number	US-9865716-B2
Application number	US-201213594289-A
Country	US
Kind code	B2
Filing date	Aug 24, 2012
Priority date	Aug 24, 2012
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.

First claim

What is claimed is:

1. A method for forming a field effect transistor (FET), the method comprising:
forming a protrusion on a surface of a substrate;
doping a lower portion of the protrusion and a portion of the substrate with a first dopant to form a drain region of a transistor, wherein the drain region extends beyond the protrusion in a first direction and a second direction opposite the first direction;
doping an upper portion of the protrusion with a second dopant to form a source region of the transistor, wherein the first and second dopants are of opposite types;
forming a transistor gate to have a planar portion and a gating surface,
wherein the gating surface surrounds a portion of the protrusion between the lower and upper portions of the protrusion,
wherein the planar portion is parallel to the surface of the substrate and located directly above the doped portion of the substrate and directly above a trench isolation feature disposed within the substrate, the trench isolation feature extending into a region of the substrate below the drain region, and
wherein an oxide layer is disposed between a gate dielectric of the planar portion and the trench isolation feature and further between the gate dielectric of the planar portion and the doped portion of the substrate; and

forming a source contact connected to the source region, a drain contact connected to the drain region, and a gate contact connected to the planar portion of the transistor gate, the drain contact being closer to the source contact than to the gate contact.

2. The method of claim 1 , wherein forming the source contact further comprises:
etching a plurality of openings in an insulating layer, a first of the openings allowing contact to a drain region, a second of the openings allowing contact to a source region, and a third of the openings allowing contact to a transistor gate; and
filling the first, second, and third of the openings with a conducting material.

3. The method of claim 1 , wherein forming the source contact, the drain contact, and the gate contact comprises forming the source contact, the drain contact, and the gate contact in a co-linear arrangement.

4. The method of claim 1 , wherein forming the source contact, the drain contact, and the gate contact comprises forming the source contact, the drain contact, and the gate contact in a right-angled arrangement.

5. The method of claim 1 , wherein the doping of the lower portion of the protrusion comprises:
doping an area of the substrate with the first dopant, the area of the substrate being adjacent to the protrusion; and
diffusing the first dopant such that some of the first dopant move laterally under the protrusion and vertically into the protrusion.

6. The method of claim 1 , further comprising, before the forming of the transistor gate:
forming the oxide layer over the trench isolation feature of the substrate, wherein the transistor gate is subsequently formed over the oxide layer.

7. A semiconductor device comprising:
a protrusion formed over a substrate;
a drain region formed over the substrate, wherein the drain region includes a lower portion of the protrusion and a doped portion of the substrate that extends beyond the protrusion in a first direction and a second direction opposite the first direction, and wherein the doped portion of the substrate that extends in the first direction is contacted by a drain contact;
a source region formed in an upper portion of the protrusion, wherein the source region is contacted by a source contact, and the source region and the drain region have opposite types of dopants;
a channel region formed between the lower and upper portions of the protrusion; and
a transistor gate having a gating surface and a planar portion,
wherein the gating surface surrounds the channel region,
wherein the planar portion is located directly above the doped portion of the substrate that extends in the second direction and directly above a trench isolation feature within the substrate, the trench isolation feature extending into a region of the substrate below the drain region,
wherein an oxide layer is disposed between a gate dielectric of the planar portion and the trench isolation feature,
wherein the planar portion is contacted by a gate contact, and
wherein, from a top view, the drain contact is closer to the source contact than to the gate contact.

8. The semiconductor device of claim 7 , wherein the oxide layer is further disposed between the doped portion of the substrate that extends in the second direction and the planar portion.

9. The semiconductor device of claim 7 , wherein the drain contact, the source contact, and gate contact are arranged co-linearly from the top view.

10. The semiconductor device of claim 7 , wherein:
the source contact and the drain contact are arranged along a first line from the top view;
the gate contact and the source contact are arranged along a second line from the top view; and
the first and second lines form a right angle.

11. The semiconductor device of claim 7 , wherein:
the drain region is generally rectangular from the top view;
the transistor gate is generally rectangular from the top view; and
the drain region and the transistor gate are arranged co-linearly from the top view.

12. The semiconductor device of claim 7 , wherein the source region, drain region, and transistor gate form a tunneling field effect transistor in which the gating surface overlaps a portion of the source region and a portion of the drain region.

13. A semiconductor device comprising:
a first tunneling field effect transistor (TFET) and a second TFET formed over a substrate, wherein the first and second TFETs further includes, respectively:
a protrusion formed over the substrate;
a drain region formed over the substrate, wherein the drain region includes a planar drain portion and a raised drain portion, the raised drain portion is a lower portion of the protrusion, and the planar drain portion further comprises a first portion and a second portion that each extend beyond the raised drain portion, wherein the first portion is contacted by a drain contact;
a source region formed in an upper portion of the protrusion, wherein the source region and the drain region have opposite types of dopants and the source region is contacted by a source contact; and
a transistor gate with a planar gate portion and a gating surface, the gating surface surrounding both a portion of the source region and a portion of the raised drain portion, and
wherein the planar gate portion of the first TFET and the planar gate portion of the second TFET are formed from a single planar structure, and the single planar structure is contacted by a gate contact and is located directly above a trench isolation feature within the substrate and further directly above the second portion of the planar drain portion with an oxide layer, the trench isolation feature extending into a region of the substrate below the drain region, and wherein the oxide layer is disposed between a gate dielectric of the planar drain portion and the trench isolation feature.

14. The semiconductor device of claim 13 , wherein the drain region of the first TFET and the drain region of the second TFET have opposite types of dopants.

15. The semiconductor device of claim 13 , wherein the gate contact, the source contact of the first TFET, and the source contact of the second TFET are arranged along a first line from a top view.

16. The semiconductor device of claim 15 , wherein:
the drain contact of the first TFET and the drain

Assignees

• Chuang Harry Hak-Lay
• Zhu Ming
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry Hak-Lay
• Zhu Ming

Classifications

• H01L21/823885

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H01L29/4238

  Electricity · mapped topic

• H01L29/0657

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic