Vertical tunneling field-effect transistor cell and fabricating the same

US9190484B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9190484-B2
Application numberUS-201313745459-A
CountryUS
Kind codeB2
Filing dateJan 18, 2013
Priority dateJan 18, 2013
Publication dateNov 17, 2015
Grant dateNov 17, 2015

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Abstract

Official abstract text for this publication.

A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.

First claim

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What is claimed is: 1. A semiconductor device comprising: a substrate formed of a semiconductor material and having a frustoconical protrusion structure with a first width protruding out of the plane of from a top surface of the substrate, the substrate formed of a semiconductor material; a drain region with a second width disposed within the substrate adjacent to the frustoconical protrusion structure and extending to a bottom portion of the frustoconical protrusion structure,…

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What does patent US9190484B2 cover?
A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is dispose…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg
What technology area does this patent fall under?
Primary CPC classification H10D30/025. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).