Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-2016268274-A1
Application number	US-201615053338-A
Country	US
Kind code	A1
Filing date	Feb 25, 2016
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

According to one embodiment, a semiconductor memory device includes a stacked body and a column. The stacked body includes a plurality of electrode layers. The column includes a semiconductor channel, a charge storage film, and a doped silicon layer. The semiconductor channel extends in the stacking direction. The semiconductor channel is a polycrystalline. An average grain size of crystals in a polycrystalline is not less than a film thickness of the semiconductor channel. The charge storage film is provided between the semiconductor channel and the electrode layers. The doped silicon layer contains a metal element and an impurity other than a metal element. The doped silicon layer is in contact with a top end of the semiconductor channel.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a stacked body including a plurality of electrode layers, an insulator being interposed between the electrode layers; and a column extending in a stacking direction in the stacked body; the column including a semiconductor channel extending in the stacking direction, the semiconductor channel being a polycrystalline, an average grain size of crystals in the polycrystalline being not less than a film thickness of the semiconductor channel, a charge storage film provided between the semiconductor channel and the electrode layers, and a doped silicon layer containing a metal element and an impurity other than a metal element, the doped silicon layer being in contact with a top end of the semiconductor channel.

2 . The device according to claim 1 , wherein the doped silicon layer contains at least one of phosphorus, arsenic, boron, and carbon as the impurity.

3 . The device according to claim 2 , wherein an impurity concentration of the doped silicon layer is higher than an impurity concentration of the semiconductor channel.

4 . The device according to claim 1 , wherein the doped silicon layer contains at least one of nickel, cobalt, and palladium as the metal element.

5 . The device according to claim 4 , wherein a metal element concentration of the doped silicon layer is higher than an impurity concentration of the semiconductor channel.

6 . The device according to claim 4 , wherein a metal element concentration of the semiconductor channel is not higher than 1×10 19 [atoms/cc].

7 . The device according to claim 1 , wherein the semiconductor channel contains a polycrystalline silicon, an average grain size of crystals in the polycrystalline silicone being not less than a film thickness of the semiconductor channel.

8 . The device according to claim 1 , further comprising a selection gate layer provided above the stacked body.

9 . The device according to claim 8 , wherein a bottom end of the doped silicon layer is positioned higher than a top face of the selection gate layer.

10 . The device according to claim 1 , wherein
the semiconductor channel is provided in a tubular shape, and the doped silicon layer is provided on an inner side of a top portion of the semiconductor channel, and contacts a side surface of the top portion of the semiconductor channel.

11 . The device according to claim 10 , wherein an impurity concentration of the top portion of the semiconductor channel is higher than an impurity concentration of a portion that faces the electrode layer in the semiconductor channel.

12 . The device according to claim 10 , further comprising
a selection gate layer provided above the stacked body, and an insulating film provided on an inner side of the semiconductor channel, wherein a boundary of a bottom end of the doped silicon layer and the insulating film is positioned higher than a top face of the selection gate layer.

13 . The device according to claim 1 , wherein
the doped silicon layer contains at least one of nickel, cobalt, and palladium as the metal element, the doped silicon layer contains at least one of phosphorus, arsenic, boron, and carbon as the impurity, and an impurity concentration of the doped silicon layer is higher than a metal element concentration of the doped silicon layer.

14 . A method for manufacturing a semiconductor memory device, comprising:
forming a stacked body on a substrate, the stacked body including a plurality of first layers and a plurality of second layers, the second layers being provided between the first layers; forming a hole penetrating through the stacked body and extending in a stacking direction of the stacked body; forming a film including a charge storage film on an inner wall of the hole; forming an amorphous semiconductor film on an inner wall of the film including the charge storage film; forming a metal silicide film on a top end of the amorphous semiconductor film; forming a semiconductor channel by single crystallizing or polycrystallizing the amorphous semiconductor film, an average grain size of crystals in the polycrystallized semiconductor channel being not less than a film thickness of the semiconductor channel; forming a doped silicon layer containing an impurity on the metal silicide film; and absorbing a metal element into the doped silicon layer, the metal element being diffused in the semiconductor channel in the MILC process.

15 . The method according to claim 14 , wherein
the doped silicon layer is provided inside an upper portion cavity of the memory hole, and on the stacked body, and after the metal element is absorbed, the doped silicon layer on the stacked body is removed, and the doped silicon layer inside the top portion cavity of the memory hole is left remaining.

16 . The method according to claim 14 , wherein, an amorphous silicon film as the amorphous semiconductor film is converted to one of a single-crystalline silicon and a polycrystalline silicon, an average grain size of crystals in the polycrystalline silicon being not less than a film thickness.

17 . The method according to claim 14 , wherein the metal silicide film contains at least one of nickel, cobalt, and palladium.

18 . The method according to claim 14 , wherein the doped silicon layer contains at least one of phosphorus, arsenic, boron, and carbon as the impurity.

Assignees

• Toshiba Kk

Inventors

• Kawai Tomoya
• Fukuzumi Yoshiaki
• Aochi Hideaki

Classifications

• H01L27/11519 Primary

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic