3D NAND array architecture

Patent metadata

Field	Value
Publication number	US-9437605-B2
Application number	US-201514857651-A
Country	US
Kind code	B2
Filing date	Sep 17, 2015
Priority date	Dec 24, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area α, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (α/pBL).

First claim

The invention claimed is:

1. A memory device on a substrate, comprising:
a multilevel stack of conductive layers, each of the layers being oriented parallel to the substrate;
a plurality of pillars oriented orthogonally to the substrate, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers;
a plurality of string select lines oriented parallel to the substrate and above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective select gate of the pillar, and all of the string select lines in the plurality overlying a single one of the conductive layers; and
a plurality of parallel bit line conductors in a layer parallel to the substrate and above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, the bit line conductors in the plurality having a pitch pBL, each of the pillars underlying one of the bit line conductors, none of the bit line conductors in the plurality of bit line conductors intersecting more than one of the pillars which underlie a single one of the string select lines,
wherein the pillars in the plurality of pillars are arranged on a regular grid having two lateral dimensions, the regular grid having a unit cell of four of the pillars A, B, C and D located at vertices of a parallelogram, and all intersecting a single one of the string select lines,
pillar B being a pillar which is nearest to pillar A in the grid,
and pillar C being a pillar which is non-collinear with pillars A and B but which is otherwise nearest pillar A in the grid,

wherein two adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL), α being the area of the unit cell.

2. The memory device of claim 1 , wherein the parallelogram is non-rectangular and is oriented such that AB is perpendicular to the bit line conductors.

3. The memory device of claim 1 , wherein the pillars in the plurality of pillars are arranged on a regular grid having two perpendicular lateral dimensions, neither of the lateral dimensions being parallel to or orthogonal to the bit line conductors.

4. The memory device of claim 1 , wherein one of the string select lines has a width in the bit line direction of Wssl,
and wherein Wssl/pBL≧30.

5. The memory device of claim 4 , wherein two adjacent ones of the string select lines each have a width in the bit line direction at least as large as Wssl,
wherein the two adjacent string select lines are spaced in the bit line direction by a spacing S,
and wherein Wssl/S≧12.

6. The memory device of claim 1 , wherein two adjacent ones of the string select lines each have a width in the bit line direction at least as large as a value Wssl,
wherein the two adjacent string select lines are spaced in the bit line direction by a spacing S,
and wherein Wssl/S≧12.

7. The memory device of claim 1 , wherein one of the conductive layers completely surrounds each of the pillars laterally that it intersects.

8. The memory device of claim 1 ,
wherein each of the conductive layers is divided laterally into a set of at least one word line;
further comprising a plurality of ground select lines disposed below the conductive layers, each of the ground select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a ground select line defining a respective ground select gate of the pillar, a number N GSL >1 of the ground select lines underlying a first one of the word lines,
wherein a number N SSLG of the string select lines superposes a first one of the ground select lines;
and wherein two adjacent ones of the ground select lines which underlie the first word line have respective widths in the bit line direction which are at least as large as (α/pBL), α being the area of the unit cell.

9. The memory device of claim 8 , wherein the number N GSL of the ground select lines underlying the first word line is between 1 and the number N SSL of the string select lines superposing the first word line, exclusive.

10. A memory device on a substrate, comprising:
a multilevel stack of conductive layers, each of the layers being divided laterally into a set of at least one word line;
a plurality of pillars oriented orthogonally to the conductive layers, each of the pillars comprising a plurality of series-connected memory cells located at cross-points between the pillars and the conductive layers;
a plurality of string select lines disposed above the conductive layers, each of the string select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a string select line defining a respective string select gate of the pillar, a number N SSL of the string select lines superposing a first one of the word lines;
a plurality of parallel bit line conductors disposed above the string select lines, each of the bit line conductors superposing a respective distinct subset of the pillars, the bit line conductors in the plurality having a pitch pBL, each of the pillars underlying one of the bit line conductors, none of the bit line conductors in the plurality of bit line conductors intersecting more than one of the pillars which underlie a single one of the string select lines; and
a plurality of ground select lines disposed below the conductive layers, each of the ground select lines intersecting a respective distinct subset of the pillars, each of the intersections of a pillar and a ground select line defining a respective ground select gate of the pillar, a number N GSL of the ground select lines underlying the first word line,
wherein the pillars in the plurality of pillars are arranged on a regular grid having two lateral dimensions, the regular grid having a unit cell of four of the pillars A, B, C and D located at vertices of a parallelogram, and all intersecting a single one of the ground select lines,
pillar B being a pillar which is nearest to pillar A in the grid,
and pillar C being a pillar which is non-collinear with pillars A and B but which is otherwise nearest pillar A in the grid,

wherein two adjacent ones of the ground select lines which underlie one of the conductive layers have respective widths in the bit line direction which are at least as large as (α/pBL), α being the area of the unit cell.

11. The memory device of claim 10 , wherein the number N GSL of the ground select lines underlying the first word line is between 1 and the number N SSL of the string select lines superposing the first word line, exclusive.

12. The memory device of claim 10 , wherein the parallelogram is non-rectangular and is oriented such that AB is perpendicular to the bit line conductors.

13. The memory device of claim 10 , wherein the pillars in the plurality of pillars are arranged on a regular grid having two perpendicular lateral dimensions, neither of the lateral dimensions being parallel to or orthogonal to the bit line conductors.

14. The memory device of claim 10 , wherein one of the ground select lines has a width in the bit line direction of Wgsl,
and wherein Wgsl/pBL≧60.

15. The memory device of claim 14 , wherein two adjacent ones of the ground select lines each have a width in the bit line direction at least as large as Wgsl,
wherein the two adjacent ground select lines are spaced in the bit line direction by a spacing Sgsl 1 ,
and wherein Wgsl/Sgsl 1 ≧24.

Assignees

• Macronix Int Co Ltd

Inventors

• Chen Shih-Hung

Classifications

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic