Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9865594-B2
Application number	US-201615015296-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Jun 16, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the wiring structures, a spacer on a sidewall of the protection pattern, and an insulating interlayer structure containing the wiring structures and having an air gap between the wiring structures.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of wiring structures spaced apart from each other;
a protection pattern on each of the wiring structures, the protection pattern including a metal nitride;
a spacer contacting a sidewall of the protection pattern, wherein a top surface of the spacer is higher than a bottom surface of the protection pattern; and
an insulating interlayer structure containing the wiring structures, the insulating interlayer structure having an air gap between the wiring structures.

2. The semiconductor device of claim 1 , wherein the protection pattern includes aluminum nitride or nitride of a noble metal.

3. The semiconductor device of claim 1 , wherein the spacer includes silicon nitride.

4. The semiconductor device of claim 1 , further comprising:
an insulating barrier layer covering upper surfaces of the protection pattern and the spacer and surrounding sidewalls of the wiring structures.

5. The semiconductor device of claim 4 , wherein the insulating barrier layer defines a bottom and a sidewall of the air gap.

6. The semiconductor device of claim 4 , wherein the insulating interlayer structure includes first and second insulating interlayers sequentially stacked, and the insulating barrier layer is formed between the first and second insulating interlayers.

7. The semiconductor device of claim 6 , wherein the first insulating interlayer covers at least a sidewall of each of the wiring structures.

8. The semiconductor device of claim 1 , further comprising:
a capping pattern on an upper surface of each of the wiring structures, the capping pattern preventing electromigration of a metal in each of the wiring structures,
wherein the protection pattern covers an upper surface and a sidewall of the capping pattern.

9. The semiconductor device of claim 8 , wherein the capping pattern comprises any one of cobalt (Co), ruthenium (Ru), tungsten (W) and cobalt tungsten phosphorus (CoWP).

10. The semiconductor device of claim 8 , wherein each of the wiring structures includes:
a metal pattern; and
a conductive barrier pattern covering a bottom and a sidewall of the metal pattern,
wherein the capping pattern is formed on an upper surface of the metal pattern.

11. The semiconductor device of claim 10 , wherein the upper surface of the metal pattern and a top surface of the conductive barrier pattern is substantially coplanar with each other,
and wherein the protection pattern covers the top surface of the conductive barrier pattern.

12. The semiconductor device of claim 10 , wherein a bottom surface of the spacer is substantially coplanar with the bottom surface of the protection pattern.

13. A semiconductor device, comprising:
a plurality of wiring structures spaced apart from each other;
a protection pattern on each of the wiring structures, the protection pattern including a metal nitride;
a spacer on a sidewall of the protection pattern, wherein a top surface of the spacer is higher than a bottom surface of the protection pattern; and
a first insulating interlayer covering a lower surface and a sidewall of each of the wiring structures,
wherein the spacer directly contacts a top surface of the first insulating interlayer.

14. The semiconductor device of claim 13 , wherein each of the wiring structures extends in a first direction, and the wiring structures are spaced apart from each other in a second direction substantially perpendicular to the first direction,
and wherein the protection pattern is disposed on only one of opposite top edge surfaces of each of the wiring structures in the second direction.

15. The semiconductor device of claim 13 , further comprising a second insulating interlayer on the first insulating interlayer,
wherein the first and second insulating interlayers form an insulating interlayer structure containing the wiring structures, the insulating interlayer structure having an air gap between the wiring structures.

16. The semiconductor device of claim 13 , wherein the spacer covers the sidewall of the protection pattern.

17. A semiconductor device, comprising:
a plurality of lower wiring structures on a substrate;
a lower insulating interlayer structure containing the lower wiring structures, the lower insulating interlayer structure having an air gap between the lower wiring structures;
a protection pattern on each of the lower wiring structures, the protection pattern including a metal nitride;
a spacer contacting a sidewall of the protection pattern, wherein a top surface of the spacer is higher than a bottom surface of the protection pattern; and
a landing via through a portion of the lower insulating interlayer structure, the landing via being electrically connected to a first lower wiring structure of the plurality of lower wiring structures,
wherein the landing via penetrates through the protection pattern on the first lower wiring structure, and contacts an upper surface of the first lower wiring structure.

18. The semiconductor device of claim 17 , further comprising:
a capping pattern on an upper surface of each of the lower wiring structures, the capping pattern preventing electromigration of a metal in each of the lower wiring structures,
wherein the protection pattern covers an upper surface and a sidewall of the capping pattern,
and wherein the landing via penetrates through the capping pattern on the first lower wiring structure.

19. The semiconductor device of claim 17 , further comprising:
an upper insulating layer on the lower insulating interlayer structure; and
an upper wiring in the upper insulating layer,
wherein the landing via contacts a bottom of the upper wiring.

20. The semiconductor device of claim 17 , wherein the landing via contacts the spacer adjacent the first lower wiring structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Siew Yong-Kong
• Ahn Sang-Hoon

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title